Loading msm/sde/sde_hw_catalog.c +15 −0 Original line number Diff line number Diff line Loading @@ -4354,6 +4354,21 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_hdr = true; sde_cfg->has_vig_p010 = true; sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0; } else if (IS_SCUBA_TARGET(hw_rev)) { sde_cfg->has_cwb_support = false; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs); clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs); } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ #define SDE_HW_VER_610 SDE_HW_VER(6, 1, 0) /* sm7250 */ #define SDE_HW_VER_630 SDE_HW_VER(6, 3, 0) /* bengal */ #define SDE_HW_VER_640 SDE_HW_VER(6, 4, 0) /* lagoon */ #define SDE_HW_VER_650 SDE_HW_VER(6, 5, 0) /* scuba */ #define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300) Loading @@ -69,6 +70,7 @@ #define IS_SAIPAN_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_610) #define IS_BENGAL_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_630) #define IS_LAGOON_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_640) #define IS_SCUBA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_650) #define SDE_HW_BLK_NAME_LEN 16 Loading Loading
msm/sde/sde_hw_catalog.c +15 −0 Original line number Diff line number Diff line Loading @@ -4354,6 +4354,21 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->has_hdr = true; sde_cfg->has_vig_p010 = true; sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0; } else if (IS_SCUBA_TARGET(hw_rev)) { sde_cfg->has_cwb_support = false; sde_cfg->has_qsync = true; sde_cfg->perf.min_prefill_lines = 24; sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; sde_cfg->sui_ns_allowed = true; sde_cfg->sui_misr_supported = true; sde_cfg->sui_block_xin_mask = 0x1; sde_cfg->has_hdr = false; sde_cfg->has_sui_blendstage = true; clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs); clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs); } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading
msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ #define SDE_HW_VER_610 SDE_HW_VER(6, 1, 0) /* sm7250 */ #define SDE_HW_VER_630 SDE_HW_VER(6, 3, 0) /* bengal */ #define SDE_HW_VER_640 SDE_HW_VER(6, 4, 0) /* lagoon */ #define SDE_HW_VER_650 SDE_HW_VER(6, 5, 0) /* scuba */ #define IS_MSM8996_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_170) #define IS_MSM8998_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_300) Loading @@ -69,6 +70,7 @@ #define IS_SAIPAN_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_610) #define IS_BENGAL_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_630) #define IS_LAGOON_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_640) #define IS_SCUBA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_650) #define SDE_HW_BLK_NAME_LEN 16 Loading