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Commit d0b42d51 authored by Shefali Jain's avatar Shefali Jain Committed by Gerrit - the friendly Code Review server
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clk: qcom: clk-debug: Add support for enable mask for debug clk 



The enable bit position could vary across targets. Add the
en_mask where the enable bit position could be supplied
for debug clock branch.

Change-Id: I9e910f53e4a13f701a3a37b640c4f72da164f6af
Signed-off-by: default avatarShefali Jain <shefjain@codeaurora.org>
parent f53bf170

drivers/clk/qcom/clk-debug.c

+8 −4
Original line number Diff line number Diff line
@@ -199,17 +199,19 @@ static void enable_debug_clks(struct clk_debug_mux *meas, u8 index) 
{

	int dbg_cc = meas->parent[index].dbg_cc;



	meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA;



	if (dbg_cc != GCC) {

		/* Not all recursive muxes have a DEBUG clock. */

		if (meas->parent[index].cbcr_offset != U32_MAX)

			regmap_update_bits(meas->regmap[dbg_cc],

					meas->parent[index].cbcr_offset,

					CBCR_ENA, CBCR_ENA);

					meas->en_mask, meas->en_mask);

	}



	/* Turn on the GCC_DEBUG_CBCR */

	regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset,

					CBCR_ENA, CBCR_ENA);

					meas->en_mask, meas->en_mask);



}
@@ -217,15 +219,17 @@ static void disable_debug_clks(struct clk_debug_mux *meas, u8 index) 
{

	int dbg_cc = meas->parent[index].dbg_cc;



	meas->en_mask = meas->en_mask ? meas->en_mask : CBCR_ENA;



	/* Turn off the GCC_DEBUG_CBCR */

	regmap_update_bits(meas->regmap[GCC], meas->cbcr_offset,

					CBCR_ENA, 0);

					meas->en_mask, 0);



	if (dbg_cc != GCC) {

		if (meas->parent[index].cbcr_offset != U32_MAX)

			regmap_update_bits(meas->regmap[dbg_cc],

					meas->parent[index].cbcr_offset,

					CBCR_ENA, 0);

					meas->en_mask, 0);

	}

}

drivers/clk/qcom/clk-debug.h

+4 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2016, 2019, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_DEBUG_H__

#define __QCOM_CLK_DEBUG_H__
@@ -88,6 +88,8 @@ struct clk_src { 
 * @num_parents:	number of parents

 * @regmap:		regmaps of debug mux

 * @priv:		private measure_clk_data to be used by debug mux

 * @en_mask:		indicates the enable bit mask at global clock

 *			controller debug mux.

 * @debug_offset:	debug mux offset.

 * @post_div_offset:	register with post-divider settings for the debug mux.

 * @cbcr_offset:	branch register to turn on debug mux.
@@ -106,6 +108,7 @@ struct clk_debug_mux { 
	int num_parents;

	struct regmap **regmap;

	void *priv;

	u32 en_mask;

	u32 debug_offset;

	u32 post_div_offset;

	u32 cbcr_offset;