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Commit d0918764 authored by Ludovic Desroches's avatar Ludovic Desroches Committed by Ulf Hansson
Browse files

mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection 



The controller has different timings for MMC_TIMING_UHS_DDR50 and
MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
lead to unexpected behavior.

Signed-off-by: default avatarLudovic Desroches <ludovic.desroches@microchip.com>
Fixes: bb5f8ea4 ("mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC")
Cc: <stable@vger.kernel.org> # 4.4+
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 923713b3

drivers/mmc/host/sdhci-of-at91.c

+10 −1
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 


#include "sdhci-pltfm.h"



#define SDMMC_MC1R	0x204

#define		SDMMC_MC1R_DDR		BIT(3)

#define SDMMC_CACR	0x230

#define		SDMMC_CACR_CAPWREN	BIT(0)

#define		SDMMC_CACR_KEY		(0x46 << 8)
@@ -103,11 +105,18 @@ static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode, 
	sdhci_set_power_noreg(host, mode, vdd);

}



void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)

{

	if (timing == MMC_TIMING_MMC_DDR52)

		sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);

	sdhci_set_uhs_signaling(host, timing);

}



static const struct sdhci_ops sdhci_at91_sama5d2_ops = {

	.set_clock		= sdhci_at91_set_clock,

	.set_bus_width		= sdhci_set_bus_width,

	.reset			= sdhci_reset,

	.set_uhs_signaling	= sdhci_set_uhs_signaling,

	.set_uhs_signaling	= sdhci_at91_set_uhs_signaling,

	.set_power		= sdhci_at91_set_power,

};