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Commit d08edd8f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.0-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi fixes from Mark Brown:
 "A collection of driver specific fixes to which the usual comments
  about them being important if you see them mostly apply (except for
  the comment fix).  The pl022 one is particularly nasty for anyone
  affected by it"

* tag 'spi-v4.0-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: pl022: Fix race in giveback() leading to driver lock-up
  spi: dw-mid: avoid potential NULL dereference
  spi: img-spfi: Verify max spfi transfer length
  spi: fix a typo in comment.
  spi: atmel: Fix interrupt setup for PDC transfers
  spi: dw: revisit FIFO size detection again
  spi: dw-pci: correct number of chip selects
  drivers: spi: ti-qspi: wait for busy bit clear before data write/read
parents eca8dac4 60c1beef

drivers/spi/spi-atmel.c

+6 −6
Original line number Diff line number Diff line
@@ -764,17 +764,17 @@ static void atmel_spi_pdc_next_xfer(struct spi_master *master, 
			(unsigned long long)xfer->rx_dma);

	}



	/* REVISIT: We're waiting for ENDRX before we start the next

	/* REVISIT: We're waiting for RXBUFF before we start the next

	 * transfer because we need to handle some difficult timing

	 * issues otherwise. If we wait for ENDTX in one transfer and

	 * then starts waiting for ENDRX in the next, it's difficult

	 * to tell the difference between the ENDRX interrupt we're

	 * actually waiting for and the ENDRX interrupt of the

	 * issues otherwise. If we wait for TXBUFE in one transfer and

	 * then starts waiting for RXBUFF in the next, it's difficult

	 * to tell the difference between the RXBUFF interrupt we're

	 * actually waiting for and the RXBUFF interrupt of the

	 * previous transfer.

	 *

	 * It should be doable, though. Just not now...

	 */

	spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));

	spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES));

	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));

}

drivers/spi/spi-dw-mid.c

+6 −0
Original line number Diff line number Diff line
@@ -139,6 +139,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws) 
				1,

				DMA_MEM_TO_DEV,

				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

	if (!txdesc)

		return NULL;



	txdesc->callback = dw_spi_dma_tx_done;

	txdesc->callback_param = dws;
@@ -184,6 +187,9 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws) 
				1,

				DMA_DEV_TO_MEM,

				DMA_PREP_INTERRUPT | DMA_CTRL_ACK);

	if (!rxdesc)

		return NULL;



	rxdesc->callback = dw_spi_dma_rx_done;

	rxdesc->callback_param = dws;

drivers/spi/spi-dw-pci.c

+2 −2
Original line number Diff line number Diff line
@@ -36,13 +36,13 @@ struct spi_pci_desc { 


static struct spi_pci_desc spi_pci_mid_desc_1 = {

	.setup = dw_spi_mid_init,

	.num_cs = 32,

	.num_cs = 5,

	.bus_num = 0,

};



static struct spi_pci_desc spi_pci_mid_desc_2 = {

	.setup = dw_spi_mid_init,

	.num_cs = 4,

	.num_cs = 2,

	.bus_num = 1,

};

drivers/spi/spi-dw.c

+2 −2
Original line number Diff line number Diff line
@@ -621,14 +621,14 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws) 
	if (!dws->fifo_len) {

		u32 fifo;



		for (fifo = 2; fifo <= 256; fifo++) {

		for (fifo = 1; fifo < 256; fifo++) {

			dw_writew(dws, DW_SPI_TXFLTR, fifo);

			if (fifo != dw_readw(dws, DW_SPI_TXFLTR))

				break;

		}

		dw_writew(dws, DW_SPI_TXFLTR, 0);



		dws->fifo_len = (fifo == 2) ? 0 : fifo - 1;

		dws->fifo_len = (fifo == 1) ? 0 : fifo;

		dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);

	}

}

drivers/spi/spi-img-spfi.c

+7 −0
Original line number Diff line number Diff line
@@ -459,6 +459,13 @@ static int img_spfi_transfer_one(struct spi_master *master, 
	unsigned long flags;

	int ret;



	if (xfer->len > SPFI_TRANSACTION_TSIZE_MASK) {

		dev_err(spfi->dev,

			"Transfer length (%d) is greater than the max supported (%d)",

			xfer->len, SPFI_TRANSACTION_TSIZE_MASK);

		return -EINVAL;

	}



	/*

	 * Stop all DMA and reset the controller if the previous transaction

	 * timed-out and never completed it's DMA.