drm/amd: Add CGS interfaces (d03846af) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/amd/amdgpu/Makefile

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Original line number	Diff line number	Diff line
		@@ -77,6 +77,9 @@ amdgpu-y += \
		amdgpu_amdkfd_gfx_v7.o \
		amdgpu_amdkfd_gfx_v8.o

		# add cgs
		amdgpu-y += amdgpu_cgs.o

		amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
		amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
		amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+8 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@
		#include <ttm/ttm_module.h>
		#include <ttm/ttm_execbuf_util.h>

		#include <drm/drmP.h>
		#include <drm/drm_gem.h>
		#include <drm/amdgpu_drm.h>

		@@ -1861,6 +1862,13 @@ int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
		extern int amdgpu_ctx_ioctl(struct drm_device dev, void data,
		struct drm_file *filp);

		/*
		* CGS
		*/
		void amdgpu_cgs_create_device(struct amdgpu_device adev);
		void amdgpu_cgs_destroy_device(void *cgs_device);


		/*
		* Core structure, functions and helpers.
		*/

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

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+327 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2015 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		*
		*/
		#include "amdgpu.h"
		#include "cgs_linux.h"

		struct amdgpu_cgs_device {
		struct cgs_device base;
		struct amdgpu_device *adev;
		};

		#define CGS_FUNC_ADEV \
		struct amdgpu_device *adev = \
		((struct amdgpu_cgs_device *)cgs_device)->adev

		static int amdgpu_cgs_gpu_mem_info(void *cgs_device, enum cgs_gpu_mem_type type,
		uint64_t mc_start, uint64_t mc_size,
		uint64_t *mem_size)
		{
		return 0;
		}

		static int amdgpu_cgs_gmap_kmem(void cgs_device, void kmem,
		uint64_t size,
		uint64_t min_offset, uint64_t max_offset,
		cgs_handle_t kmem_handle, uint64_t mcaddr)
		{
		return 0;
		}

		static int amdgpu_cgs_gunmap_kmem(void *cgs_device, cgs_handle_t kmem_handle)
		{
		return 0;
		}

		static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device,
		enum cgs_gpu_mem_type type,
		uint64_t size, uint64_t align,
		uint64_t min_offset, uint64_t max_offset,
		cgs_handle_t *handle)
		{
		return 0;
		}

		static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd,
		cgs_handle_t *handle)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_gmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
		uint64_t *mcaddr)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_gunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_kmap_gpu_mem(void *cgs_device, cgs_handle_t handle,
		void **map)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_kunmap_gpu_mem(void *cgs_device, cgs_handle_t handle)
		{
		/* TODO */
		return 0;
		}

		static uint32_t amdgpu_cgs_read_register(void *cgs_device, unsigned offset)
		{
		/* TODO */
		return 0;
		}

		static void amdgpu_cgs_write_register(void *cgs_device, unsigned offset,
		uint32_t value)
		{
		/* TODO */
		return;
		}

		static uint32_t amdgpu_cgs_read_ind_register(void *cgs_device,
		enum cgs_ind_reg space,
		unsigned index)
		{
		/* TODO */
		return 0;
		}

		static void amdgpu_cgs_write_ind_register(void *cgs_device,
		enum cgs_ind_reg space,
		unsigned index, uint32_t value)
		{
		/* TODO */
		return;
		}

		static uint8_t amdgpu_cgs_read_pci_config_byte(void *cgs_device, unsigned addr)
		{
		/* TODO */
		return 0;
		}

		static uint16_t amdgpu_cgs_read_pci_config_word(void *cgs_device, unsigned addr)
		{
		/* TODO */
		return 0;
		}

		static uint32_t amdgpu_cgs_read_pci_config_dword(void *cgs_device,
		unsigned addr)
		{
		/* TODO */
		return 0;
		}

		static void amdgpu_cgs_write_pci_config_byte(void *cgs_device, unsigned addr,
		uint8_t value)
		{
		/* TODO */
		return;
		}

		static void amdgpu_cgs_write_pci_config_word(void *cgs_device, unsigned addr,
		uint16_t value)
		{
		/* TODO */
		return;
		}

		static void amdgpu_cgs_write_pci_config_dword(void *cgs_device, unsigned addr,
		uint32_t value)
		{
		/* TODO */
		return;
		}

		static const void amdgpu_cgs_atom_get_data_table(void cgs_device,
		unsigned table, uint16_t *size,
		uint8_t frev, uint8_t crev)
		{
		/* TODO */
		return NULL;
		}

		static int amdgpu_cgs_atom_get_cmd_table_revs(void *cgs_device, unsigned table,
		uint8_t frev, uint8_t crev)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_atom_exec_cmd_table(void *cgs_device, unsigned table,
		void *args)
		{
		/* TODO */
		return 0;
		}


		static int amdgpu_cgs_create_pm_request(void cgs_device, cgs_handle_t request)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_destroy_pm_request(void *cgs_device, cgs_handle_t request)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_set_pm_request(void *cgs_device, cgs_handle_t request,
		int active)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_pm_request_clock(void *cgs_device, cgs_handle_t request,
		enum cgs_clock clock, unsigned freq)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_pm_request_engine(void *cgs_device, cgs_handle_t request,
		enum cgs_engine engine, int powered)
		{
		/* TODO */
		return 0;
		}



		static int amdgpu_cgs_pm_query_clock_limits(void *cgs_device,
		enum cgs_clock clock,
		struct cgs_clock_limits *limits)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_set_camera_voltages(void *cgs_device, uint32_t mask,
		const uint32_t *voltages)
		{
		DRM_ERROR("not implemented");
		return -EPERM;
		}

		static int amdgpu_cgs_add_irq_source(void *cgs_device, unsigned src_id,
		unsigned num_types,
		cgs_irq_source_set_func_t set,
		cgs_irq_handler_func_t handler,
		void *private_data)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_irq_get(void *cgs_device, unsigned src_id, unsigned type)
		{
		/* TODO */
		return 0;
		}

		static int amdgpu_cgs_irq_put(void *cgs_device, unsigned src_id, unsigned type)
		{
		/* TODO */
		return 0;
		}

		static const struct cgs_ops amdgpu_cgs_ops = {
		amdgpu_cgs_gpu_mem_info,
		amdgpu_cgs_gmap_kmem,
		amdgpu_cgs_gunmap_kmem,
		amdgpu_cgs_alloc_gpu_mem,
		amdgpu_cgs_free_gpu_mem,
		amdgpu_cgs_gmap_gpu_mem,
		amdgpu_cgs_gunmap_gpu_mem,
		amdgpu_cgs_kmap_gpu_mem,
		amdgpu_cgs_kunmap_gpu_mem,
		amdgpu_cgs_read_register,
		amdgpu_cgs_write_register,
		amdgpu_cgs_read_ind_register,
		amdgpu_cgs_write_ind_register,
		amdgpu_cgs_read_pci_config_byte,
		amdgpu_cgs_read_pci_config_word,
		amdgpu_cgs_read_pci_config_dword,
		amdgpu_cgs_write_pci_config_byte,
		amdgpu_cgs_write_pci_config_word,
		amdgpu_cgs_write_pci_config_dword,
		amdgpu_cgs_atom_get_data_table,
		amdgpu_cgs_atom_get_cmd_table_revs,
		amdgpu_cgs_atom_exec_cmd_table,
		amdgpu_cgs_create_pm_request,
		amdgpu_cgs_destroy_pm_request,
		amdgpu_cgs_set_pm_request,
		amdgpu_cgs_pm_request_clock,
		amdgpu_cgs_pm_request_engine,
		amdgpu_cgs_pm_query_clock_limits,
		amdgpu_cgs_set_camera_voltages
		};

		static const struct cgs_os_ops amdgpu_cgs_os_ops = {
		amdgpu_cgs_import_gpu_mem,
		amdgpu_cgs_add_irq_source,
		amdgpu_cgs_irq_get,
		amdgpu_cgs_irq_put
		};

		void amdgpu_cgs_create_device(struct amdgpu_device adev)
		{
		struct amdgpu_cgs_device *cgs_device =
		kmalloc(sizeof(*cgs_device), GFP_KERNEL);

		if (!cgs_device) {
		DRM_ERROR("Couldn't allocate CGS device structure\n");
		return NULL;
		}

		cgs_device->base.ops = &amdgpu_cgs_ops;
		cgs_device->base.os_ops = &amdgpu_cgs_os_ops;
		cgs_device->adev = adev;

		return cgs_device;
		}

		void amdgpu_cgs_destroy_device(void *cgs_device)
		{
		kfree(cgs_device);
		}

drivers/gpu/drm/amd/include/cgs_common.h

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File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/include/cgs_linux.h

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		/*
		* Copyright 2015 Advanced Micro Devices, Inc.
		*
		* Permission is hereby granted, free of charge, to any person obtaining a
		* copy of this software and associated documentation files (the "Software"),
		* to deal in the Software without restriction, including without limitation
		* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		* and/or sell copies of the Software, and to permit persons to whom the
		* Software is furnished to do so, subject to the following conditions:
		*
		* The above copyright notice and this permission notice shall be included in
		* all copies or substantial portions of the Software.
		*
		* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
		* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		* OTHER DEALINGS IN THE SOFTWARE.
		*
		*
		*/
		#ifndef _CGS_LINUX_H
		#define _CGS_LINUX_H

		#include "cgs_common.h"

		/**
		* cgs_import_gpu_mem() - Import dmabuf handle
		* @cgs_device: opaque device handle
		* @dmabuf_fd: DMABuf file descriptor
		* @handle: memory handle (output)
		*
		* Must be called in the process context that dmabuf_fd belongs to.
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_import_gpu_mem_t)(void cgs_device, int dmabuf_fd,
		cgs_handle_t *handle);

		/**
		* cgs_irq_source_set_func() - Callback for enabling/disabling interrupt sources
		* @private_data: private data provided to cgs_add_irq_source
		* @src_id: interrupt source ID
		* @type: interrupt type
		* @enabled: 0 = disable source, non-0 = enable source
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_irq_source_set_func_t)(void private_data,
		unsigned src_id, unsigned type,
		int enabled);

		/**
		* cgs_irq_handler_func() - Interrupt handler callback
		* @private_data: private data provided to cgs_add_irq_source
		* @src_id: interrupt source ID
		* @iv_entry: pointer to raw ih ring entry
		*
		* This callback runs in interrupt context.
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_irq_handler_func_t)(void private_data,
		unsigned src_id, const uint32_t *iv_entry);

		/**
		* cgs_add_irq_source() - Add an IRQ source
		* @cgs_device: opaque device handle
		* @src_id: interrupt source ID
		* @num_types: number of interrupt types that can be independently enabled
		* @set: callback function to enable/disable an interrupt type
		* @handler: interrupt handler callback
		* @private_data: private data to pass to callback functions
		*
		* The same IRQ source can be added only once. Adding an IRQ source
		* indicates ownership of that IRQ source and all its IRQ types.
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_add_irq_source_t)(void cgs_device, unsigned src_id,
		unsigned num_types,
		cgs_irq_source_set_func_t set,
		cgs_irq_handler_func_t handler,
		void *private_data);

		/**
		* cgs_irq_get() - Request enabling an IRQ source and type
		* @cgs_device: opaque device handle
		* @src_id: interrupt source ID
		* @type: interrupt type
		*
		* cgs_irq_get and cgs_irq_put calls must be balanced. They count
		* "references" to IRQ sources.
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_irq_get_t)(void cgs_device, unsigned src_id, unsigned type);

		/**
		* cgs_irq_put() - Indicate IRQ source is no longer needed
		* @cgs_device: opaque device handle
		* @src_id: interrupt source ID
		* @type: interrupt type
		*
		* cgs_irq_get and cgs_irq_put calls must be balanced. They count
		* "references" to IRQ sources. Even after cgs_irq_put is called, the
		* IRQ handler may still be called if there are more refecences to
		* the IRQ source.
		*
		* Return: 0 on success, -errno otherwise
		*/
		typedef int (cgs_irq_put_t)(void cgs_device, unsigned src_id, unsigned type);

		struct cgs_os_ops {
		cgs_import_gpu_mem_t import_gpu_mem;

		/* IRQ handling */
		cgs_add_irq_source_t add_irq_source;
		cgs_irq_get_t irq_get;
		cgs_irq_put_t irq_put;
		};

		#define cgs_import_gpu_mem(dev,dmabuf_fd,handle) \
		CGS_OS_CALL(import_gpu_mem,dev,dmabuf_fd,handle)
		#define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \
		CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler, \
		private_data)
		#define cgs_irq_get(dev,src_id,type) \
		CGS_OS_CALL(irq_get,dev,src_id,type)
		#define cgs_irq_put(dev,src_id,type) \
		CGS_OS_CALL(irq_put,dev,src_id,type)

		#endif /* _CGS_LINUX_H */