Loading qcom/lito-coresight.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -2590,6 +2590,9 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <4>; pinctrl-names = "cti-trigout-pctrl"; pinctrl-0 = <&trigout_a>; }; cti3: cti@6013000 { Loading qcom/lito-pinctrl.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,19 @@ interrupt-controller; #interrupt-cells = <2>; trigout_a: trigout_a { mux { pins = "gpio63"; function = "qdss_cti"; }; config { pins = "gpio63"; drive-strength = <2>; bias-disable; }; }; qupv3_se2_2uart_pins: qupv3_se2_2uart_pins { qupv3_se2_2uart_active: qupv3_se2_2uart_active { mux { Loading Loading
qcom/lito-coresight.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -2590,6 +2590,9 @@ clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; qcom,cti-gpio-trigout = <4>; pinctrl-names = "cti-trigout-pctrl"; pinctrl-0 = <&trigout_a>; }; cti3: cti@6013000 { Loading
qcom/lito-pinctrl.dtsi +13 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,19 @@ interrupt-controller; #interrupt-cells = <2>; trigout_a: trigout_a { mux { pins = "gpio63"; function = "qdss_cti"; }; config { pins = "gpio63"; drive-strength = <2>; bias-disable; }; }; qupv3_se2_2uart_pins: qupv3_se2_2uart_pins { qupv3_se2_2uart_active: qupv3_se2_2uart_active { mux { Loading