Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cfc7588a authored by Alim Akhtar's avatar Alim Akhtar Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynos7: Fix CMU TOP1 block 



As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.

Signed-off-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent fa9f3a52

drivers/clk/samsung/clk-exynos7.c

+15 −9
Original line number Diff line number Diff line
@@ -365,12 +365,15 @@ CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0", 
#define MUX_SEL_TOP13			0x020C

#define MUX_SEL_TOP1_FSYS0		0x0224

#define MUX_SEL_TOP1_FSYS1		0x0228

#define MUX_SEL_TOP1_FSYS11		0x022C

#define DIV_TOP13			0x060C

#define DIV_TOP1_FSYS0			0x0624

#define DIV_TOP1_FSYS1			0x0628

#define DIV_TOP1_FSYS11			0x062C

#define ENABLE_ACLK_TOP13		0x080C

#define ENABLE_SCLK_TOP1_FSYS0		0x0A24

#define ENABLE_SCLK_TOP1_FSYS1		0x0A28

#define ENABLE_SCLK_TOP1_FSYS11		0x0A2C



/* List of parent clocks for Muxes in CMU_TOP1 */

PNAME(mout_top1_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
@@ -397,12 +400,15 @@ static unsigned long top1_clk_regs[] __initdata = { 
	MUX_SEL_TOP13,

	MUX_SEL_TOP1_FSYS0,

	MUX_SEL_TOP1_FSYS1,

	MUX_SEL_TOP1_FSYS11,

	DIV_TOP13,

	DIV_TOP1_FSYS0,

	DIV_TOP1_FSYS1,

	DIV_TOP1_FSYS11,

	ENABLE_ACLK_TOP13,

	ENABLE_SCLK_TOP1_FSYS0,

	ENABLE_SCLK_TOP1_FSYS1,

	ENABLE_SCLK_TOP1_FSYS11,

};



static struct samsung_mux_clock top1_mux_clks[] __initdata = {
@@ -425,12 +431,12 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = { 
	MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),

	MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),



	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),

	MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),

	MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,

		MUX_SEL_TOP1_FSYS0, 28, 2),



	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),

	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),

	MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),

	MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),

};



static struct samsung_div_clock top1_div_clks[] __initdata = {
@@ -440,26 +446,26 @@ static struct samsung_div_clock top1_div_clks[] __initdata = { 
		DIV_TOP13, 28, 4),



	DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",

		DIV_TOP1_FSYS0, 24, 4),

		DIV_TOP1_FSYS0, 16, 10),

	DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",

		DIV_TOP1_FSYS0, 28, 4),



	DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",

		DIV_TOP1_FSYS1, 24, 4),

		DIV_TOP1_FSYS11, 0, 10),

	DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",

		DIV_TOP1_FSYS1, 28, 4),

		DIV_TOP1_FSYS11, 12, 10),

};



static struct samsung_gate_clock top1_gate_clks[] __initdata = {

	GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",

		ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),

		ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),

	GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",

		ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),



	GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",

		ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),

		ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),

	GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",

		ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),

		ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),

};



static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {