Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cf769bd8 authored by Mika Westerberg's avatar Mika Westerberg Committed by Linus Walleij
Browse files

pinctrl: intel: Make offset to interrupt status register configurable 



Some GPIO blocks have the interrupt status (GPI_IS) offset different
than it normally is, so make it configurable. If no offset is specified
we use the default.

While there remove two unused constants from the core driver.

Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 13960072

drivers/pinctrl/intel/pinctrl-intel.c

+12 −8
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ 


#define PADBAR				0x00c

#define GPI_IS				0x100

#define GPI_GPE_STS			0x140

#define GPI_GPE_EN			0x160



#define PADOWN_BITS			4

#define PADOWN_SHIFT(p)			((p) % 8 * PADOWN_BITS)
@@ -818,7 +816,7 @@ static void intel_gpio_irq_ack(struct irq_data *d) 
	community = intel_get_community(pctrl, pin);

	if (community) {

		const struct intel_padgroup *padgrp;

		unsigned gpp, gpp_offset;

		unsigned gpp, gpp_offset, is_offset;



		padgrp = intel_community_get_padgroup(community, pin);

		if (!padgrp)
@@ -826,9 +824,10 @@ static void intel_gpio_irq_ack(struct irq_data *d) 


		gpp = padgrp->reg_num;

		gpp_offset = padgroup_offset(padgrp, pin);

		is_offset = community->is_offset + gpp * 4;



		raw_spin_lock(&pctrl->lock);

		writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);

		writel(BIT(gpp_offset), community->regs + is_offset);

		raw_spin_unlock(&pctrl->lock);

	}

}
@@ -843,7 +842,7 @@ static void intel_gpio_irq_enable(struct irq_data *d) 
	community = intel_get_community(pctrl, pin);

	if (community) {

		const struct intel_padgroup *padgrp;

		unsigned gpp, gpp_offset;

		unsigned gpp, gpp_offset, is_offset;

		unsigned long flags;

		u32 value;
@@ -853,10 +852,11 @@ static void intel_gpio_irq_enable(struct irq_data *d) 


		gpp = padgrp->reg_num;

		gpp_offset = padgroup_offset(padgrp, pin);

		is_offset = community->is_offset + gpp * 4;



		raw_spin_lock_irqsave(&pctrl->lock, flags);

		/* Clear interrupt status first to avoid unexpected interrupt */

		writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);

		writel(BIT(gpp_offset), community->regs + is_offset);



		value = readl(community->regs + community->ie_offset + gpp * 4);

		value |= BIT(gpp_offset);
@@ -991,7 +991,8 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, 
		const struct intel_padgroup *padgrp = &community->gpps[gpp];

		unsigned long pending, enabled, gpp_offset;



		pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4);

		pending = readl(community->regs + community->is_offset +

				padgrp->reg_num * 4);

		enabled = readl(community->regs + community->ie_offset +

				padgrp->reg_num * 4);
@@ -1241,6 +1242,9 @@ int intel_pinctrl_probe(struct platform_device *pdev, 
		community->regs = regs;

		community->pad_regs = regs + padbar;



		if (!community->is_offset)

			community->is_offset = GPI_IS;



		ret = intel_pinctrl_add_padgroups(pctrl, community);

		if (ret)

			return ret;
@@ -1356,7 +1360,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl) 
		for (gpp = 0; gpp < community->ngpps; gpp++) {

			/* Mask and clear all interrupts */

			writel(0, base + community->ie_offset + gpp * 4);

			writel(0xffff, base + GPI_IS + gpp * 4);

			writel(0xffff, base + community->is_offset + gpp * 4);

		}

	}

}

drivers/pinctrl/intel/pinctrl-intel.h

+3 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ struct intel_padgroup { 
 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it

 *                  is assumed that the host owns the pin (rather than

 *                  ACPI).

 * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the

 *             default (%0x100).

 * @ie_offset: Register offset of GPI_IE from @regs.

 * @pin_base: Starting pin of pins in this community

 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
@@ -98,6 +100,7 @@ struct intel_community { 
	unsigned padown_offset;

	unsigned padcfglock_offset;

	unsigned hostown_offset;

	unsigned is_offset;

	unsigned ie_offset;

	unsigned pin_base;

	unsigned gpp_size;