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Commit cf2e9c7b authored by Kukjin Kim's avatar Kukjin Kim
Browse files

Merge branch 'next-samsung-clkdev-fix' into next-samsung-cleanup

parents b5930b83 e4805599

arch/arm/Kconfig

+6 −0
Original line number Diff line number Diff line
@@ -682,6 +682,7 @@ config ARCH_S3C2410 
	select GENERIC_GPIO

	select ARCH_HAS_CPUFREQ

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARCH_USES_GETTIMEOFFSET

	select HAVE_S3C2410_I2C if I2C

	help
@@ -699,6 +700,7 @@ config ARCH_S3C64XX 
	select CPU_V6

	select ARM_VIC

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select NO_IOPORT

	select ARCH_USES_GETTIMEOFFSET

	select ARCH_HAS_CPUFREQ
@@ -723,6 +725,7 @@ config ARCH_S5P64X0 
	select CPU_V6

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select HAVE_S3C2410_WATCHDOG if WATCHDOG

	select GENERIC_CLOCKEVENTS

	select HAVE_SCHED_CLOCK
@@ -736,6 +739,7 @@ config ARCH_S5PC100 
	bool "Samsung S5PC100"

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select CPU_V7

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_USES_GETTIMEOFFSET
@@ -751,6 +755,7 @@ config ARCH_S5PV210 
	select ARCH_SPARSEMEM_ENABLE

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARM_L1_CACHE_SHIFT_6

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS
@@ -767,6 +772,7 @@ config ARCH_EXYNOS4 
	select ARCH_SPARSEMEM_ENABLE

	select GENERIC_GPIO

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select ARCH_HAS_CPUFREQ

	select GENERIC_CLOCKEVENTS

	select HAVE_S3C_RTC if RTC_CLASS

arch/arm/mach-exynos4/clock.c

+57 −120

File changed.

Preview size limit exceeded, changes collapsed.

arch/arm/mach-exynos4/include/mach/clkdev.h

0 → 100644
+7 −0
Original line number Diff line number Diff line 
#ifndef __MACH_CLKDEV_H__

#define __MACH_CLKDEV_H__



#define __clk_get(clk) ({ 1; })

#define __clk_put(clk) do {} while (0)



#endif

arch/arm/mach-s3c2412/clock.c

+3 −33
Original line number Diff line number Diff line
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) 


static struct clk clk_erefclk = {

	.name		= "erefclk",

	.id		= -1,

};



static struct clk clk_urefclk = {

	.name		= "urefclk",

	.id		= -1,

};



static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent) 


static struct clk clk_usysclk = {

	.name		= "usysclk",

	.id		= -1,

	.parent		= &clk_xtal,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = { 
static struct clk clk_mrefclk = {

	.name		= "mrefclk",

	.parent		= &clk_xtal,

	.id		= -1,

};



static struct clk clk_mdivclk = {

	.name		= "mdivclk",

	.parent		= &clk_xtal,

	.id		= -1,

};



static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) 


static struct clk clk_usbsrc = {

	.name		= "usbsrc",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_usbsrc,

		.set_rate	= s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) 


static struct clk clk_msysclk = {

	.name		= "msysclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_msysclk,

	},
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent) 


static struct clk clk_armclk = {

	.name		= "armclk",

	.id		= -1,

	.parent		= &clk_msysclk,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) 


static struct clk clk_uart = {

	.name		= "uartclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_uart,

		.set_rate	= s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) 


static struct clk clk_i2s = {

	.name		= "i2sclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_i2s,

		.set_rate	= s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) 


static struct clk clk_cam = {

	.name		= "camif-upll",	/* same as 2440 name */

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_cam,

		.set_rate	= s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = { 
static struct clk init_clocks_disable[] = {

	{

		.name		= "nand",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_NAND,

	}, {

		.name		= "sdi",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_SDI,

	}, {

		.name		= "adc",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_ADC,

	}, {

		.name		= "i2c",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_IIC,

	}, {

		.name		= "iis",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_IIS,

	}, {

		.name		= "spi",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = { 
static struct clk init_clocks[] = {

	{

		.name		= "dma",

		.id		= 0,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA0,

	}, {

		.name		= "dma",

		.id		= 1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA1,

	}, {

		.name		= "dma",

		.id		= 2,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA2,

	}, {

		.name		= "dma",

		.id		= 3,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_DMA3,

	}, {

		.name		= "lcd",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_LCDC,

	}, {

		.name		= "gpio",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_GPIO,

	}, {

		.name		= "usb-host",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USBH,

	}, {

		.name		= "usb-device",

		.id		= -1,

		.parent		= &clk_h,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USBD,

	}, {

		.name		= "timers",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_PWMT,

	}, {

		.name		= "uart",

		.id		= 0,

		.devname	= "s3c2412-uart.0",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART0,

	}, {

		.name		= "uart",

		.id		= 1,

		.devname	= "s3c2412-uart.1",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART1,

	}, {

		.name		= "uart",

		.id		= 2,

		.devname	= "s3c2412-uart.2",

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_UART2,

	}, {

		.name		= "rtc",

		.id		= -1,

		.parent		= &clk_p,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_RTC,

	}, {

		.name		= "watchdog",

		.id		= -1,

		.parent		= &clk_p,

		.ctrlbit	= 0,

	}, {

		.name		= "usb-bus-gadget",

		.id		= -1,

		.parent		= &clk_usb_bus,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USB_DEV48,

	}, {

		.name		= "usb-bus-host",

		.id		= -1,

		.parent		= &clk_usb_bus,

		.enable		= s3c2412_clkcon_enable,

		.ctrlbit	= S3C2412_CLKCON_USB_HOST48,

arch/arm/mach-s3c2416/clock.c

+5 −5
Original line number Diff line number Diff line
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { 
	[0] = {

		.clk = {

			.name	= "hsmmc-div",

			.id	= 0,

			.devname	= "s3c-sdhci.0",

			.parent	= &clk_esysclk.clk,

		},

		.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { 
	[1] = {

		.clk = {

			.name	= "hsmmc-div",

			.id	= 1,

			.devname	= "s3c-sdhci.1",

			.parent	= &clk_esysclk.clk,

		},

		.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = { 
static struct clksrc_clk hsmmc_mux[] = {

	[0] = {

		.clk	= {

			.id	= 0,

			.name	= "hsmmc-if",

			.devname	= "s3c-sdhci.0",

			.ctrlbit = (1 << 6),

			.enable = s3c2443_clkcon_enable_s,

		},
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { 
	},

	[1] = {

		.clk	= {

			.id	= 1,

			.name	= "hsmmc-if",

			.devname	= "s3c-sdhci.1",

			.ctrlbit = (1 << 12),

			.enable = s3c2443_clkcon_enable_s,

		},
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = { 


static struct clk hsmmc0_clk = {

	.name		= "hsmmc",

	.id		= 0,

	.devname	= "s3c-sdhci.0",

	.parent		= &clk_h,

	.enable		= s3c2443_clkcon_enable_h,

	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,