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Commit cf0ab2cd authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: handle cg in CI dpm code 



Clockgating needs to be disabled around certain parts
of dpm setup otherwise the smc gets into a bad state
and dpm doesn't work properly.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a0f38609

drivers/gpu/drm/radeon/ci_dpm.c

+36 −0
Original line number Original line Diff line number Diff line
@@ -155,6 +155,8 @@ extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 
						     struct atom_voltage_table *voltage_table);

						     struct atom_voltage_table *voltage_table);

extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);

extern void cik_update_cg(struct radeon_device *rdev,

			  u32 block, bool enable);





static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,

static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,

					 struct atom_voltage_table_entry *voltage_table,

					 struct atom_voltage_table_entry *voltage_table,
@@ -4492,6 +4494,13 @@ int ci_dpm_enable(struct radeon_device *rdev) 
	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

	int ret;

	int ret;





	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	if (ci_is_smc_running(rdev))

	if (ci_is_smc_running(rdev))

		return -EINVAL;

		return -EINVAL;

	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

	if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
@@ -4611,6 +4620,13 @@ int ci_dpm_enable(struct radeon_device *rdev) 




	ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);

	ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);





	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), true);



	ci_update_current_ps(rdev, boot_ps);

	ci_update_current_ps(rdev, boot_ps);





	return 0;

	return 0;
@@ -4621,6 +4637,12 @@ void ci_dpm_disable(struct radeon_device *rdev) 
	struct ci_power_info *pi = ci_get_pi(rdev);

	struct ci_power_info *pi = ci_get_pi(rdev);

	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;

	struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;





	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	if (!ci_is_smc_running(rdev))

	if (!ci_is_smc_running(rdev))

		return;

		return;
@@ -4649,6 +4671,13 @@ int ci_dpm_set_power_state(struct radeon_device *rdev) 
	struct radeon_ps *old_ps = &pi->current_rps;

	struct radeon_ps *old_ps = &pi->current_rps;

	int ret;

	int ret;





	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), false);



	ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);

	ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);

	if (pi->pcie_performance_request)

	if (pi->pcie_performance_request)

		ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);

		ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
@@ -4710,6 +4739,13 @@ int ci_dpm_set_power_state(struct radeon_device *rdev) 
		return ret;

		return ret;

	}

	}





	cik_update_cg(rdev, (RADEON_CG_BLOCK_GFX |

			     RADEON_CG_BLOCK_MC |

			     RADEON_CG_BLOCK_SDMA |

			     RADEON_CG_BLOCK_BIF |

			     RADEON_CG_BLOCK_UVD |

			     RADEON_CG_BLOCK_HDP), true);



	return 0;

	return 0;

}

}