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Commit cece638b authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: fix compilation errors in sde_encoder"

parents d6a53bfe 4c8e4a2a

drivers/gpu/drm/msm/sde/sde_crtc.c

+7 −18
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>

 *
@@ -4207,6 +4207,7 @@ static int _sde_crtc_check_secure_state_smmu_translation(struct drm_crtc *crtc, 
	int fb_ns, int fb_sec, int fb_sec_dir)

{

	struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;

	struct drm_encoder *encoder;

	int is_video_mode = false;



	drm_for_each_encoder_mask(encoder, crtc->dev,
@@ -4330,7 +4331,6 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
	uint32_t secure;

	uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;

	int rc;

	bool is_video_mode = false;



	if (!crtc || !state) {

		SDE_ERROR("invalid arguments\n");
@@ -4481,8 +4481,7 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state, 
		int cnt)

{

	int rc = 0, i, z_pos;

	int left_zpos_cnt = 0, right_zpos_cnt = 0;

	int mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);

	u32 zpos_cnt = 0;



	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
@@ -4515,21 +4514,11 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state, 
			SDE_ERROR("> %d plane stages assigned\n",

					SDE_STAGE_MAX - SDE_STAGE_0);

			return -EINVAL;

		} else if (pstates[i].drm_pstate->crtc_x < mixer_width) {

			if (left_zpos_cnt == 2) {

				SDE_ERROR("> 2 planes @ stage %d on left\n",

					z_pos);

		} else if (zpos_cnt == 2) {

			SDE_ERROR("> 2 planes @ stage %d\n", z_pos);

			return -EINVAL;

			}

			left_zpos_cnt++;



		} else {

			if (right_zpos_cnt == 2) {

				SDE_ERROR("> 2 planes @ stage %d on right\n",

					z_pos);

				return -EINVAL;

			}

			right_zpos_cnt++;

			zpos_cnt++;

		}



		pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;

drivers/gpu/drm/msm/sde/sde_encoder.c

+10 −16
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>

 *
@@ -996,12 +996,14 @@ static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc, 
}



static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,

	struct drm_crtc_state *crtc_state, struct sde_encoder_virt *sde_enc,

	struct drm_crtc_state *crtc_state, struct sde_kms *sde_kms,

	struct drm_crtc_state *crtc_state,

	struct drm_connector_state *conn_state,

	struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,

	struct sde_connector *sde_conn,

	struct sde_connector_state *sde_conn_state)

{

	int ret = 0;

	struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;



	if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {

		struct msm_display_topology *topology = NULL;
@@ -1078,7 +1080,6 @@ static int sde_encoder_virt_atomic_check( 
	struct sde_connector_state *sde_conn_state = NULL;

	struct sde_crtc_state *sde_crtc_state = NULL;

	enum sde_rm_topology_name old_top;

	int i = 0;

	int ret = 0;



	if (!drm_enc || !crtc_state || !conn_state) {
@@ -1121,7 +1122,7 @@ static int sde_encoder_virt_atomic_check( 
		return ret;



	ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,

			sde_enc, crtc_state, sde_kms, sde_conn, sde_conn_state);

			conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);



	ret = sde_connector_roi_v1_check_roi(conn_state);

	if (ret) {
@@ -2536,17 +2537,10 @@ static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc, 
		SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,

				SDE_EVTLOG_ERROR);

		goto end;

	}



	/*

	 * if we are in ON but a frame was just kicked off,

	 * ignore the IDLE event, it's probably a stale timer event

	 */

	if (sde_enc->frame_busy_mask[0]) {

		SDE_ERROR_ENC(sde_enc,

				"sw_event:%d, rc:%d frame pending\n",

				sw_event, sde_enc->rc_state);

	} else if (sde_crtc_frame_pending(sde_enc->crtc) > 1) {

		SDE_ERROR_ENC(sde_enc, "skip idle entry");

		SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,

			sde_crtc_frame_pending(sde_enc->crtc),

			SDE_EVTLOG_ERROR);

		goto end;

	}

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+2 −2
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 */



#define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
@@ -3934,7 +3934,7 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev) 
	if (rc)

		goto end;



	rc = sde_parse_dt(np, sde_cfg);

	rc = sde_top_parse_dt(np, sde_cfg);

	if (rc)

		goto end;

drivers/gpu/drm/msm/sde/sde_plane.c

+80 −80
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.

 * Copyright (C) 2014-2019 The Linux Foundation. All rights reserved.

 * Copyright (C) 2013 Red Hat

 * Author: Rob Clark <robdclark@gmail.com>

 *
@@ -2699,8 +2699,9 @@ void sde_plane_set_error(struct drm_plane *plane, bool error) 
static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,

	struct sde_plane_state *pstate, const struct sde_format *fmt)

{

	if (psde->pipe_hw->ops.setup_sys_cache &&

		(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE))) {

	if (!psde->pipe_hw->ops.setup_sys_cache ||

	    !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))

		return;



	SDE_DEBUG("features:0x%x rotation:0x%x\n",

		__func__, psde->features, pstate->rotation);
@@ -2718,7 +2719,6 @@ static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde, 
		pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |

			SSPP_SYS_CACHE_SCID;

	}

	}



	psde->pipe_hw->ops.setup_sys_cache(

		psde->pipe_hw, &pstate->sc_cfg);
@@ -2774,6 +2774,65 @@ static void _sde_plane_map_prop_to_dirty_bits(void) 
		SDE_PLANE_DIRTY_ALL;

}



static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,

	struct sde_rect *src, struct sde_rect *dst)

{

	u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;

	u32 downscale = (src->h * 1000)/dst->h;



	return (downscale > max_downscale) ? false : true;

}



static void _sde_plane_setup_uidle(struct drm_crtc *crtc,

	struct sde_plane *psde, struct sde_plane_state *pstate,

	struct sde_rect *src, struct sde_rect *dst)

{

	struct sde_hw_pipe_uidle_cfg cfg;

	u32 line_time = sde_get_linetime(&crtc->mode); /* nS */

	u32 fal1_target_idle_time_ns =

		psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */

	u32 fal10_target_idle_time_ns =

		psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */

	u32 fal10_threshold =

		psde->catalog->uidle_cfg.fal10_threshold; /* uS */



	if (line_time && fal10_threshold && fal10_target_idle_time_ns &&

		fal1_target_idle_time_ns) {

		cfg.enable = _sde_plane_allow_uidle(psde, src, dst);

		cfg.fal10_threshold = fal10_threshold;

		cfg.fal10_exit_threshold = fal10_threshold + 2;

		cfg.fal1_threshold = 1 +

			(fal1_target_idle_time_ns*1000/line_time*2)/1000;

		cfg.fal_allowed_threshold = fal10_threshold +

			(fal10_target_idle_time_ns*1000/line_time*2)/1000;

	} else {

		SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",

			line_time, fal10_threshold, fal10_target_idle_time_ns,

			fal1_target_idle_time_ns);

		cfg.enable = false;

		cfg.fal10_threshold = 0;

		cfg.fal1_threshold = 0;

		cfg.fal_allowed_threshold = 0;

	}



	SDE_DEBUG_PLANE(psde,

		"tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",

			cfg.fal10_threshold, cfg.fal10_exit_threshold,

			cfg.fal1_threshold, cfg.fal_allowed_threshold);

	SDE_DEBUG_PLANE(psde,

		"times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",

			line_time, fal1_target_idle_time_ns,

			fal10_target_idle_time_ns,

			psde->catalog->uidle_cfg.max_dwnscale);

	SDE_EVT32(cfg.enable, cfg.fal10_threshold, cfg.fal10_exit_threshold,

		cfg.fal1_threshold, cfg.fal_allowed_threshold,

		psde->catalog->uidle_cfg.max_dwnscale);



	psde->pipe_hw->ops.setup_uidle(

		psde->pipe_hw, &cfg,

		pstate->multirect_index);

}



static void _sde_plane_update_secure_session(struct sde_plane *psde,

	struct sde_plane_state *pstate)

{
@@ -2891,65 +2950,6 @@ static void _sde_plane_update_roi_config(struct drm_plane *plane, 
				pstate->multirect_mode);

}



static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,

	struct sde_rect *src, struct sde_rect *dst)

{

	u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;

	u32 downscale = (src->h * 1000)/dst->h;



	return (downscale > max_downscale) ? false : true;

}



static void _sde_plane_setup_uidle(struct drm_crtc *crtc,

	struct sde_plane *psde, struct sde_plane_state *pstate,

	struct sde_rect *src, struct sde_rect *dst)

{

	struct sde_hw_pipe_uidle_cfg cfg;

	u32 line_time = sde_get_linetime(&crtc->mode); /* nS */

	u32 fal1_target_idle_time_ns =

		psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */

	u32 fal10_target_idle_time_ns =

		psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */

	u32 fal10_threshold =

		psde->catalog->uidle_cfg.fal10_threshold; /* uS */



	if (line_time && fal10_threshold && fal10_target_idle_time_ns &&

		fal1_target_idle_time_ns) {

		cfg.enable = _sde_plane_allow_uidle(psde, src, dst);

		cfg.fal10_threshold = fal10_threshold;

		cfg.fal10_exit_threshold = fal10_threshold + 2;

		cfg.fal1_threshold = 1 +

			(fal1_target_idle_time_ns*1000/line_time*2)/1000;

		cfg.fal_allowed_threshold = fal10_threshold +

			(fal10_target_idle_time_ns*1000/line_time*2)/1000;

	} else {

		SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",

			line_time, fal10_threshold, fal10_target_idle_time_ns,

			fal1_target_idle_time_ns);

		cfg.enable = false;

		cfg.fal10_threshold = 0;

		cfg.fal1_threshold = 0;

		cfg.fal_allowed_threshold = 0;

	}



	SDE_DEBUG_PLANE(psde,

		"tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",

			cfg.fal10_threshold, cfg.fal10_exit_threshold,

			cfg.fal1_threshold, cfg.fal_allowed_threshold);

	SDE_DEBUG_PLANE(psde,

		"times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",

			line_time, fal1_target_idle_time_ns,

			fal10_target_idle_time_ns,

			psde->catalog->uidle_cfg.max_dwnscale);

	SDE_EVT32(cfg.enable, cfg.fal10_threshold, cfg.fal10_exit_threshold,

		cfg.fal1_threshold, cfg.fal_allowed_threshold,

		psde->catalog->uidle_cfg.max_dwnscale);



	psde->pipe_hw->ops.setup_uidle(

		psde->pipe_hw, &cfg,

		pstate->multirect_index);

}



static void _sde_plane_update_format_and_rects(struct sde_plane *psde,

	struct sde_plane_state *pstate, const struct sde_format *fmt)

{
@@ -3170,7 +3170,7 @@ static int sde_plane_sspp_atomic_update(struct drm_plane *plane, 
	psde->is_rt_pipe = (sde_crtc_get_client_type(crtc) != NRT_CLIENT);

	_sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);



	sde_plane_update_properties(plane, crtc, fb);

	_sde_plane_update_properties(plane, crtc, fb);



	return 0;

}