Merge "ARM: dts: msm: Add jtagv8 devices for lagoon"

		interrupt-parent = <&intc>;

	};

	jtag_mm0: jtagmm@7040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7040000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};

	jtag_mm1: jtagmm@7140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7140000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};

	jtag_mm2: jtagmm@7240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7240000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};

	jtag_mm3: jtagmm@7340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7340000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};

	jtag_mm4: jtagmm@7440000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7440000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU4>;

	};

	jtag_mm5: jtagmm@7540000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7540000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU5>;

	};

	jtag_mm6: jtagmm@7640000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7640000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU6>;

	};

	jtag_mm7: jtagmm@7740000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x7740000 0x1000>;

		reg-names = "etm-base";

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};

	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";