Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ce8ac552 authored by Jilai Wang's avatar Jilai Wang
Browse files

msm: npu: Power off npu until cpc power is off 



Even after shutdown irq is received, NPUQ6 may not finish power
collapse yet. So it is necessary to wait until npu cpc is off
before turn off npu power.

Change-Id: I86a193354020f3c74c4260d4cbbfe16cd14aa7e3
Signed-off-by: default avatarJilai Wang <jilaiw@codeaurora.org>
parent 773b595b

drivers/media/platform/msm/npu/npu_common.h

+1 −1
Original line number Diff line number Diff line
@@ -245,7 +245,7 @@ struct npu_device { 
	struct npu_io_data core_io;

	struct npu_io_data tcm_io;

	struct npu_io_data cc_io;

	struct npu_io_data qdsp_io;

	struct npu_io_data tcsr_io;

	struct npu_io_data apss_shared_io;

	struct npu_io_data qfprom_io;

drivers/media/platform/msm/npu/npu_dev.c

+10 −10
Original line number Diff line number Diff line
@@ -2174,23 +2174,23 @@ static int npu_probe(struct platform_device *pdev) 
		res->start, npu_dev->cc_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "qdsp");

		IORESOURCE_MEM, "tcsr");

	if (!res) {

		NPU_ERR("unable to get qdsp resource\n");

		NPU_ERR("unable to get tcsr_mutex resource\n");

		rc = -ENODEV;

		goto error_get_dev_num;

	}

	npu_dev->qdsp_io.size = resource_size(res);

	npu_dev->qdsp_io.phy_addr = res->start;

	npu_dev->qdsp_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->qdsp_io.size);

	if (unlikely(!npu_dev->qdsp_io.base)) {

		NPU_ERR("unable to map qdsp\n");

	npu_dev->tcsr_io.size = resource_size(res);

	npu_dev->tcsr_io.phy_addr = res->start;

	npu_dev->tcsr_io.base = devm_ioremap(&pdev->dev, res->start,

					npu_dev->tcsr_io.size);

	if (unlikely(!npu_dev->tcsr_io.base)) {

		NPU_ERR("unable to map tcsr\n");

		rc = -ENOMEM;

		goto error_get_dev_num;

	}

	NPU_DBG("qdsp phy address=0x%llx virt=%pK\n",

		res->start, npu_dev->qdsp_io.base);

	NPU_DBG("tcsr phy address=0x%llx virt=%pK\n",

		res->start, npu_dev->tcsr_io.base);



	res = platform_get_resource_byname(pdev,

		IORESOURCE_MEM, "apss_shared");

drivers/media/platform/msm/npu/npu_hw.h

+3 −0
Original line number Diff line number Diff line
@@ -72,4 +72,7 @@ 
#define NPU_CC_NPU_MASTERn_WDOG_BITE_IRQ_OWNER(n) (0x0006010+4*(n))

#define NPU_CC_NPU_MASTERn_WDOG_BITE_IRQ_STATUS(n) (0x00009030+0x1000*(n))



#define TCSR_NPU_CPC_PWR_ON (0x0003700C)

#define NPU_CPC_PWR_ON (1 << 0)



#endif /* NPU_HW_H */

drivers/media/platform/msm/npu/npu_hw_access.c

+2 −8
Original line number Diff line number Diff line
@@ -34,20 +34,14 @@ void npu_core_reg_write(struct npu_device *npu_dev, uint32_t off, uint32_t val) 
	__iowmb();

}



uint32_t npu_qdsp_reg_read(struct npu_device *npu_dev, uint32_t off)

uint32_t npu_tcsr_reg_read(struct npu_device *npu_dev, uint32_t off)

{

	uint32_t ret = 0;



	ret = readl(npu_dev->qdsp_io.base + off);

	ret = readl_relaxed(npu_dev->tcsr_io.base + off);

	return ret;

}



void npu_qdsp_reg_write(struct npu_device *npu_dev, uint32_t off, uint32_t val)

{

	writel_relaxed(val, npu_dev->qdsp_io.base + off);

	__iowmb();

}



uint32_t npu_apss_shared_reg_read(struct npu_device *npu_dev, uint32_t off)

{

	uint32_t ret = 0;

drivers/media/platform/msm/npu/npu_hw_access.h

+1 −2
Original line number Diff line number Diff line
@@ -50,8 +50,7 @@ typedef irqreturn_t (*intr_hdlr_fn)(int32_t irq, void *ptr); 
 */

uint32_t npu_core_reg_read(struct npu_device *npu_dev, uint32_t off);

void npu_core_reg_write(struct npu_device *npu_dev, uint32_t off, uint32_t val);

uint32_t npu_qdsp_reg_read(struct npu_device *npu_dev, uint32_t off);

void npu_qdsp_reg_write(struct npu_device *npu_dev, uint32_t off, uint32_t val);

uint32_t npu_tcsr_reg_read(struct npu_device *npu_dev, uint32_t off);

uint32_t npu_apss_shared_reg_read(struct npu_device *npu_dev, uint32_t off);

void npu_apss_shared_reg_write(struct npu_device *npu_dev, uint32_t off,

	uint32_t val);