Loading drivers/bus/mhi/core/mhi_pm.c +6 −3 Original line number Diff line number Diff line Loading @@ -376,14 +376,17 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { struct mhi_ring *tre_ring = &mhi_chan->tre_ring; if (mhi_chan->db_cfg.reset_req) { write_lock_irq(&mhi_chan->lock); if (mhi_chan->db_cfg.reset_req) mhi_chan->db_cfg.db_mode = true; write_unlock_irq(&mhi_chan->lock); } read_lock_irq(&mhi_chan->lock); /* only ring DB if ring is not empty */ if (tre_ring->base && tre_ring->wp != tre_ring->rp) mhi_ring_chan_db(mhi_cntrl, mhi_chan); write_unlock_irq(&mhi_chan->lock); read_unlock_irq(&mhi_chan->lock); } mhi_cntrl->wake_put(mhi_cntrl, false); Loading Loading
drivers/bus/mhi/core/mhi_pm.c +6 −3 Original line number Diff line number Diff line Loading @@ -376,14 +376,17 @@ int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { struct mhi_ring *tre_ring = &mhi_chan->tre_ring; if (mhi_chan->db_cfg.reset_req) { write_lock_irq(&mhi_chan->lock); if (mhi_chan->db_cfg.reset_req) mhi_chan->db_cfg.db_mode = true; write_unlock_irq(&mhi_chan->lock); } read_lock_irq(&mhi_chan->lock); /* only ring DB if ring is not empty */ if (tre_ring->base && tre_ring->wp != tre_ring->rp) mhi_ring_chan_db(mhi_cntrl, mhi_chan); write_unlock_irq(&mhi_chan->lock); read_unlock_irq(&mhi_chan->lock); } mhi_cntrl->wake_put(mhi_cntrl, false); Loading