Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ce20269d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] SMTC: Fix recursion in instant IPI replay code.
  [MIPS] BCM1480: Fix setting of irq affinity.
  [MIPS] do_page_fault() needs to use raw_smp_processor_id().
  [MIPS] SMTC: Fix false trigger of debug code on single VPE.
  [MIPS] SMTC: irq_{enter,leave} and kstats keeping for relayed timer ints.
  [MIPS] lockdep: Deal with interrupt disable hazard in TRACE_IRQFLAGS
  [MIPS] lockdep: Handle interrupts in R3000 style c0_status register.
  [MIPS] MV64340: Add missing prototype for mv64340_irq_init().
  [MIPS] MT: MIPS_MT_SMTC_INSTANT_REPLAY currently conflicts with PREEMPT.
  [MIPS] EV64120: Include <asm/irq.h> to fix warning.
  [MIPS] Ocelot: Fix warning.
  [MIPS] Ocelot: Give PMON_v1_setup a proper prototype.
parents 9754c5f6 8a1e97ee

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -1606,7 +1606,7 @@ config MIPS_MT_FPAFF 


config MIPS_MT_SMTC_INSTANT_REPLAY

	bool "Low-latency Dispatch of Deferred SMTC IPIs"

	depends on MIPS_MT_SMTC

	depends on MIPS_MT_SMTC && !PREEMPT

	default y

	help

	  SMTC pseudo-interrupts between TCs are deferred and queued

arch/mips/gt64120/momenco_ocelot/prom.c

+0 −1
Original line number Diff line number Diff line
@@ -32,7 +32,6 @@ void __init prom_init(void) 
	char **arg = (char **) fw_arg1;

	char **env = (char **) fw_arg2;

	struct callvectors *cv = (struct callvectors *) fw_arg3;

	uint32_t tmp;

	int i;



	/* save the PROM vectors for debugging use */

arch/mips/gt64120/momenco_ocelot/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static char reset_reason; 
static void __init setup_l3cache(unsigned long size);



/* setup code for a handoff from a version 1 PMON 2000 PROM */

void PMON_v1_setup()

static void PMON_v1_setup(void)

{

	/* A wired TLB entry for the GT64120A and the serial port. The

	   GT64120A is going to be hit on every IRQ anyway - there's

arch/mips/kernel/entry.S

+5 −1
Original line number Diff line number Diff line
@@ -121,7 +121,11 @@ FEXPORT(restore_partial) # restore partial frame 
	SAVE_AT

	SAVE_TEMP

	LONG_L	v0, PT_STATUS(sp)

	and	v0, 1

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

	and	v0, ST0_IEP

#else

	and	v0, ST0_IE

#endif

	beqz	v0, 1f

	jal	trace_hardirqs_on

	b	2f

arch/mips/kernel/genex.S

+31 −0
Original line number Diff line number Diff line
@@ -128,6 +128,37 @@ handle_vcei: 


	.align  5

NESTED(handle_int, PT_SIZE, sp)

#ifdef CONFIG_TRACE_IRQFLAGS

	/*

	 * Check to see if the interrupted code has just disabled

	 * interrupts and ignore this interrupt for now if so.

	 *

	 * local_irq_disable() disables interrupts and then calls

	 * trace_hardirqs_off() to track the state. If an interrupt is taken

	 * after interrupts are disabled but before the state is updated

	 * it will appear to restore_all that it is incorrectly returning with

	 * interrupts disabled

	 */

	.set	push

	.set	noat

	mfc0	k0, CP0_STATUS

#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)

	and	k0, ST0_IEP

	bnez	k0, 1f



	mfc0	k0, EP0_EPC

	.set	noreorder

	j	k0

	rfe

#else

	and	k0, ST0_IE

	bnez	k0, 1f



	eret

#endif

1:

	.set pop

#endif

	SAVE_ALL

	CLI

	TRACE_IRQS_OFF