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Commit cdc3a3a6 authored by Urvashi Agrawal's avatar Urvashi Agrawal Committed by Harshdeep Dhatt
Browse files

ARM: dts: msm: Add GPU dtsi for kona 



Add device tree file for adreno a650.

Change-Id: Ic503291f930cdd61f7d495457b60886ac1d2e596
Signed-off-by: default avatarUrvashi Agrawal <urvaagra@codeaurora.org>
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
parent 9812e86a

arch/arm64/boot/dts/qcom/kona-gpu.dtsi

0 → 100644
+360 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



&soc {

	pil_gpu: qcom,kgsl-hyp {

		compatible = "qcom,pil-tz-generic";

		qcom,pas-id = <13>;

		qcom,firmware-name = "a650_zap";

	};



	msm_bus: qcom,kgsl-busmon {

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};



	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_vbif";

		qcom,src-dst-ports = <26 512>;

		operating-points-v2 = <&suspendable_ddr_bw_opp_table>;

	};



	gpu_opp_table: gpu-opp-table {

		compatible = "operating-points-v2";



		opp-700000000 {

			opp-hz = /bits/ 64 <700000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;

		};



		opp-670000000 {

			opp-hz = /bits/ 64 <670000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;

		};



		opp-625000000 {

			opp-hz = /bits/ 64 <625000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;

		};



		opp-480000000 {

			opp-hz = /bits/ 64 <480000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;

		};



		opp-381000000 {

			opp-hz = /bits/ 64 <381000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;

		};



		opp-290000000 {

			opp-hz = /bits/ 64 <290000000>;

			opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;

		};

	};



	msm_gpu: qcom,kgsl-3d0@3d00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,

			<0x3de0000 0x10000>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc";

		interrupts = <0 300 IRQ_TYPE_NONE>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;



		qcom,chipid = <0x06050000>;



		qcom,initial-pwrlevel = <5>;



		qcom,idle-timeout = <1000000>; /* msecs */



		qcom,no-nap;



		qcom,highest-bank-bit = <16>;



		qcom,min-access-length = <32>;



		qcom,ubwc-mode = <4>;



		qcom,snapshot-size = <1048576>; /* bytes */



		qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */



		qcom,tsens-name = "tsens_tz_sensor12";

		#cooling-cells = <2>;



		qcom,pm-qos-active-latency = <44>;



		clocks = <&clock_gpucc GPU_CC_CXO_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&clock_gpucc GPU_CC_CX_GMU_CLK>,

			<&clock_gpucc GPU_CC_AHB_CLK>,

			<&clock_cpucc L3_GPU_VOTE_CLK>;



		clock-names = "rbbmtimer_clk", "mem_clk",

				"mem_iface_clk", "gmu_clk",

				"gpu_cc_ahb", "l3_vote";



		qcom,isense-clk-on-level = <1>;



		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		//qcom,bus-control;

		qcom,msm-bus,name = "grp3d";

		qcom,bus-width = <32>;

		qcom,msm-bus,num-cases = <13>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<26 512 0 0>,

				<26 512 0 400000>,      /* 1 bus=100 */

				<26 512 0 600000>,      /* 2 bus=150 */

				<26 512 0 800000>,      /* 3 bus=200 */

				<26 512 0 1200000>,     /* 4 bus=300 */

				<26 512 0 1648000>,     /* 5 bus=412 */

				<26 512 0 2188000>,     /* 6 bus=547 */

				<26 512 0 2724000>,     /* 7 bus=681 */

				<26 512 0 3072000>,     /* 8 bus=768 */

				<26 512 0 4068000>,     /* 9 bus=1017 */

				<26 512 0 5184000>,     /* 10 bus=1296 */

				<26 512 0 6220000>,     /* 11 bus=1555 */

				<26 512 0 7216000>;     /* 12 bus=1804 */



		/* GDSC regulator names */

		regulator-names = "vddcx", "vdd";

		/* GDSC oxili regulators */

		vddcx-supply = <&gpu_cx_gdsc>;

		vdd-supply = <&gpu_gx_gdsc>;



		/* GPU OPP data */

		operating-points-v2 = <&gpu_opp_table>;



		qcom,l3-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,l3-pwrlevels";



			qcom,l3-pwrlevel@0 {

				reg = <0>;

				qcom,l3-freq = <0>;

			};



			qcom,l3-pwrlevel@1 {

				reg = <1>;

				qcom,l3-freq = <864000000>;

			};



			qcom,l3-pwrlevel@2 {

				reg = <2>;

				qcom,l3-freq = <1344000000>;

			};

		};



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-mempools";



			/* 4K Page Pool configuration */

			qcom,gpu-mempool@0 {

				reg = <0>;

				qcom,mempool-page-size = <4096>;

				qcom,mempool-reserved = <2048>;

				qcom,mempool-allocate;

			};

			/* 8K Page Pool configuration */

			qcom,gpu-mempool@1 {

				reg = <1>;

				qcom,mempool-page-size = <8192>;

				qcom,mempool-reserved = <1024>;

				qcom,mempool-allocate;

			};

			/* 64K Page Pool configuration */

			qcom,gpu-mempool@2 {

				reg = <2>;

				qcom,mempool-page-size = <65536>;

				qcom,mempool-reserved = <256>;

			};

			/* 1M Page Pool configuration */

			qcom,gpu-mempool@3 {

				reg = <3>;

				qcom,mempool-page-size = <1048576>;

				qcom,mempool-reserved = <32>;

			};

		};



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";



			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <700000000>;

				qcom,bus-freq = <12>;

				qcom,bus-min = <10>;

				qcom,bus-max = <12>;

			};



			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <670000000>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <625000000>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <480000000>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <381000000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};



			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <290000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};



			qcom,gpu-pwrlevel@6 {

				reg = <6>;

				qcom,gpu-freq = <0>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};



	kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {

		compatible = "qcom,kgsl-smmu-v2";



		reg = <0x03da0000 0x10000>;

		/* CB5(ATOS) & CB5/6/7 are protected by HYP */

		qcom,protect = <0xa0000 0xc000>;



		clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,

			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;



		clock-names = "iface_clk", "mem_clk", "mem_iface_clk";



		qcom,secure_align_mask = <0xfff>;

		qcom,global_pt;

		qcom,retention;

		qcom,hyp_secure_alloc;



		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_user";

			iommus = <&kgsl_smmu 0x0 0x401>;

			qcom,iommu-dma = "disabled";

			qcom,gpu-offset = <0xa8000>;

		};



		gfx3d_secure: gfx3d_secure {

			compatible = "qcom,smmu-kgsl-cb";

			label = "gfx3d_secure";

			iommus = <&kgsl_smmu 0x2 0x400>;

			qcom,iommu-dma = "disabled";

		};

	};



	gmu: qcom,gmu@3d6a000 {

		label = "kgsl-gmu";

		compatible = "qcom,gpu-gmu";



		reg = <0x3d6a000 0x30000>,

			<0xb290000 0x10000>,

			<0xb490000 0x10000>;

		reg-names = "kgsl_gmu_reg",

			"kgsl_gmu_pdc_cfg",

			"kgsl_gmu_pdc_seq";



		interrupts = <0 304 IRQ_TYPE_NONE>, <0 305 IRQ_TYPE_NONE>;

		interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";



		qcom,msm-bus,name = "cnoc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 10036 0 0>,		/* CNOC off */

			<26 10036 0 100>;	/* CNOC on */



		regulator-names = "vddcx", "vdd";

		vddcx-supply = <&gpu_cx_gdsc>;

		vdd-supply = <&gpu_gx_gdsc>;



		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,

				<&clock_gpucc GPU_CC_CXO_CLK>,

				<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

				<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

				<&clock_gpucc GPU_CC_AHB_CLK>;



		clock-names = "gmu_clk", "cxo_clk", "axi_clk",

				"memnoc_clk", "gpu_cc_ahb";



		/* AOP mailbox for sending ACD enable and disable messages */

		mboxes = <&qmp_aop 0>;

		mbox-names = "aop";



		qcom,gmu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gmu-pwrlevels";



			/* GMU power levels must go from lowest to highest */

			qcom,gmu-pwrlevel@0 {

				reg = <0>;

				qcom,gmu-freq = <0>;

			};



			qcom,gmu-pwrlevel@1 {

				reg = <1>;

				qcom,gmu-freq = <200000000>;

			};

		};



		gmu_user: gmu_user {

			compatible = "qcom,smmu-gmu-user-cb";

			iommus = <&kgsl_smmu 0x4 0x400>;

			qcom,iommu-dma = "disabled";

		};



		gmu_kernel: gmu_kernel {

			compatible = "qcom,smmu-gmu-kernel-cb";

			iommus = <&kgsl_smmu 0x5 0x400>;

			qcom,iommu-dma = "disabled";

		};

	};

};

arch/arm64/boot/dts/qcom/kona.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -3211,7 +3211,6 @@ 
#include "kona-sde-pll.dtsi"



#include "kona-pm.dtsi"



#include "kona-camera.dtsi"

#include "kona-qupv3.dtsi"

#include "kona-audio.dtsi"
@@ -3219,3 +3218,4 @@ 
#include "kona-vidc.dtsi"

#include "kona-cvp.dtsi"

#include "kona-npu.dtsi"

#include "kona-gpu.dtsi"