ARM: dts: msm: Add QUPv3 SE and GPI DT nodes for lagoon (cda36acb) · Commits · e / devices / android_kernel_fairphone_FP4

qcom/lagoon-pinctrl.dtsi

+313 −8

Original line number	Diff line number	Diff line
		@@ -57,12 +57,12 @@
		qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
		qupv3_se7_2uart_active: qupv3_se7_2uart_active {
		mux {
		pins = "gpio28", "gpio27";
		pins = "gpio27", "gpio28";
		function = "qup11";
		};

		config {
		pins = "gpio28", "gpio27";
		pins = "gpio27", "gpio28";
		drive-strength = <2>;
		bias-disable;
		};
		@@ -70,12 +70,12 @@

		qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
		mux {
		pins = "gpio28", "gpio27";
		pins = "gpio27", "gpio28";
		function = "gpio";
		};

		config {
		pins = "gpio28", "gpio27";
		pins = "gpio27", "gpio28";
		drive-strength = <2>;
		bias-pull-down;
		};
		@@ -85,12 +85,12 @@
		qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
		qupv3_se9_2uart_active: qupv3_se9_2uart_active {
		mux {
		pins = "gpio26", "gpio25";
		pins = "gpio25", "gpio26";
		function = "qup13";
		};

		config {
		pins = "gpio26", "gpio25";
		pins = "gpio25", "gpio26";
		drive-strength = <2>;
		bias-disable;
		};
		@@ -98,16 +98,321 @@

		qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
		mux {
		pins = "gpio26", "gpio25";
		pins = "gpio25", "gpio26";
		function = "gpio";
		};

		config {
		pins = "gpio26", "gpio25";
		pins = "gpio25", "gpio26";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		qupv3_se1_4uart_pins: qupv3_se1_4uart_pins {
		qupv3_se1_ctsrx: qupv3_se1_ctsrx {
		mux {
		pins = "gpio61", "gpio64";
		function = "qup01";
		};

		config {
		pins = "gpio61", "gpio64";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se1_rts: qupv3_se1_rts {
		mux {
		pins = "gpio62";
		function = "qup01";
		};

		config {
		pins = "gpio62";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se1_tx: qupv3_se1_tx {
		mux {
		pins = "gpio63";
		function = "qup01";
		};

		config {
		pins = "gpio63";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
		qupv3_se0_i2c_active: qupv3_se0_i2c_active {
		mux {
		pins = "gpio0", "gpio1";
		function = "qup00";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
		mux {
		pins = "gpio0", "gpio1";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
		mux {
		pins = "gpio45", "gpio46";
		function = "qup02";
		};

		config {
		pins = "gpio45", "gpio46";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
		mux {
		pins = "gpio45", "gpio46";
		function = "gpio";
		};

		config {
		pins = "gpio45", "gpio46";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
		mux {
		pins = "gpio13", "gpio14";
		function = "qup10";
		};

		config {
		pins = "gpio13", "gpio14";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
		mux {
		pins = "gpio13", "gpio14";
		function = "gpio";
		};

		config {
		pins = "gpio13", "gpio14";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
		mux {
		pins = "gpio27", "gpio28";
		function = "qup11";
		};

		config {
		pins = "gpio27", "gpio28";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
		mux {
		pins = "gpio27", "gpio28";
		function = "gpio";
		};

		config {
		pins = "gpio27", "gpio28";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
		qupv3_se8_i2c_active: qupv3_se8_i2c_active {
		mux {
		pins = "gpio19", "gpio20";
		function = "qup12";
		};

		config {
		pins = "gpio19", "gpio20";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
		mux {
		pins = "gpio19", "gpio20";
		function = "gpio";
		};

		config {
		pins = "gpio19", "gpio20";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
		qupv3_se10_i2c_active: qupv3_se10_i2c_active {
		mux {
		pins = "gpio4", "gpio5";
		function = "qup14";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-pull-up;
		};
		};

		qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
		mux {
		pins = "gpio4", "gpio5";
		function = "gpio";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-disable;
		};
		};
		};

		qupv3_se0_spi_pins: qupv3_se0_spi_pins {
		qupv3_se0_spi_active: qupv3_se0_spi_active {
		mux {
		pins = "gpio0", "gpio1",
		"gpio2", "gpio3";
		function = "qup00";
		};

		config {
		pins = "gpio0", "gpio1",
		"gpio2", "gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
		mux {
		pins = "gpio0", "gpio1",
		"gpio2", "gpio3";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1",
		"gpio2", "gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		qupv3_se2_spi_pins: qupv3_se2_spi_pins {
		qupv3_se2_spi_active: qupv3_se2_spi_active {
		mux {
		pins = "gpio45", "gpio46",
		"gpio56", "gpio57";
		function = "qup02";
		};

		config {
		pins = "gpio45", "gpio46",
		"gpio56", "gpio57";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
		mux {
		pins = "gpio45", "gpio46",
		"gpio56", "gpio57";
		function = "gpio";
		};

		config {
		pins = "gpio45", "gpio46",
		"gpio56", "gpio57";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		qupv3_se6_spi_pins: qupv3_se6_spi_pins {
		qupv3_se6_spi_active: qupv3_se6_spi_active {
		mux {
		pins = "gpio13", "gpio14",
		"gpio15", "gpio16";
		function = "qup10";
		};

		config {
		pins = "gpio13", "gpio14",
		"gpio15", "gpio16";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
		mux {
		pins = "gpio13", "gpio14",
		"gpio15", "gpio16";
		function = "gpio";
		};

		config {
		pins = "gpio13", "gpio14",
		"gpio15", "gpio16";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};
		};
		};

qcom/lagoon-qupv3.dtsi

+280 −4

Original line number	Diff line number	Diff line
		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/* QUPv3_1 wrapper instance */
		/* QUPv3 SE Instances
		* North 0 : SE 0
		* North 1 : SE 1
		* North 2 : SE 2
		* South 0 : SE 6
		* South 1 : SE 7
		* South 2 : SE 8
		* South 3 : SE 9
		* South 4 : SE 10
		*/

		/* QUPv3_0 wrapper instance : North QUP */
		qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x2000>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-bus-ids =
		<MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
		<MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
		iommus = <&apps_smmu 0x43 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
		qcom,iommu-dma = "fastmap";
		};

		gpi_dma0: qcom,gpi-dma@800000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0x800000 0x60000>;
		reg-names = "gpi-top";
		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <10>;
		qcom,gpii-mask = <0x1f>;
		qcom,ev-factor = <2>;
		iommus = <&apps_smmu 0x56 0x0>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
		status = "ok";
		};

		qupv3_se0_i2c: i2c@880000 {
		compatible = "qcom,i2c-geni";
		reg = <0x880000 0x4000>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 0 3 64 0>,
		<&gpi_dma0 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_i2c_active>;
		pinctrl-1 = <&qupv3_se0_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se0_spi: spi@880000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x880000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se0_spi_active>;
		pinctrl-1 = <&qupv3_se0_spi_sleep>;
		interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		dmas = <&gpi_dma0 0 0 1 64 0>,
		<&gpi_dma0 1 0 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se1_4uart: qcom,qup_uart@884000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x884000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
		<&qupv3_se1_tx>;
		pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
		<&qupv3_se1_tx>;
		interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
		<&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,wakeup-byte = <0xFD>;
		status = "disabled";
		};

		qupv3_se2_i2c: i2c@888000 {
		compatible = "qcom,i2c-geni";
		reg = <0x888000 0x4000>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se2_spi: spi@888000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x888000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_spi_active>;
		pinctrl-1 = <&qupv3_se2_spi_sleep>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		dmas = <&gpi_dma0 0 2 1 64 0>,
		<&gpi_dma0 1 2 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		/* QUPv3_1 wrapper instance : South QUP */
		qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x9c0000 0x2000>;
		@@ -11,10 +163,75 @@
		<MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
		iommus = <&apps_smmu 0x4c3 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
		qcom,iommu-dma = "atomic";
		qcom,iommu-dma = "fastmap";
		};

		gpi_dma1: qcom,gpi-dma@900000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0x900000 0x60000>;
		reg-names = "gpi-top";
		interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <10>;
		qcom,gpii-mask = <0x3f>;
		qcom,ev-factor = <2>;
		iommus = <&apps_smmu 0x4d6 0x0>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
		status = "ok";
		};

		qupv3_se6_i2c: i2c@980000 {
		compatible = "qcom,i2c-geni";
		reg = <0x980000 0x4000>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 0 3 64 0>,
		<&gpi_dma1 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se6_spi: spi@980000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x980000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_spi_active>;
		pinctrl-1 = <&qupv3_se6_spi_sleep>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 0 1 64 0>,
		<&gpi_dma1 1 0 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		/* RUMI Debug UART Instance */
		qupv3_se7_2uart: qcom,qup_uart@984000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x984000 0x4000>;
		@@ -31,7 +248,46 @@
		status = "disabled";
		};

		/* Debug UART Instance */
		qupv3_se7_i2c: i2c@984000 {
		compatible = "qcom,i2c-geni";
		reg = <0x984000 0x4000>;
		interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 1 3 64 0>,
		<&gpi_dma1 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se8_i2c: i2c@988000 {
		compatible = "qcom,i2c-geni";
		reg = <0x988000 0x4000>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 2 3 64 0>,
		<&gpi_dma1 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_i2c_active>;
		pinctrl-1 = <&qupv3_se8_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se9_2uart: qcom,qup_uart@98c000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x98c000 0x4000>;
		@@ -45,6 +301,26 @@
		pinctrl-1 = <&qupv3_se9_2uart_sleep>;
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "ok";
		};

		qupv3_se10_i2c: i2c@990000 {
		compatible = "qcom,i2c-geni";
		reg = <0x990000 0x4000>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 4 3 64 0>,
		<&gpi_dma1 1 4 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se10_i2c_active>;
		pinctrl-1 = <&qupv3_se10_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};
		};