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Commit cd9b0b0b authored by Sudheer Papothi's avatar Sudheer Papothi Committed by Gerrit - the friendly Code Review server
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ASoC: tx-macro: Allow regcache sync during clock enablement 



Allow regcache sync during clock enable to make sure the registers
are in proper state before the usecase.

Change-Id: I8a9214e460c7f77759d1956e0e7e2d6b2f5b3d3a
Signed-off-by: default avatarSudheer Papothi <spapothi@codeaurora.org>
parent 9503ada7

asoc/codecs/bolero/tx-macro.c

+4 −4
Original line number Diff line number Diff line
@@ -234,11 +234,11 @@ static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, 
		}

		bolero_clk_rsc_fs_gen_request(tx_priv->dev,

					true);

		if (tx_priv->tx_mclk_users == 0) {

		regcache_mark_dirty(regmap);

		regcache_sync_region(regmap,

				TX_START_OFFSET,

				TX_MAX_OFFSET);

		if (tx_priv->tx_mclk_users == 0) {

			/* 9.6MHz MCLK, set value 0x00 if other frequency */

			regmap_update_bits(regmap,

				BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);