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Commit ccb09a8e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux into drm-next 

It looks like you missed my last 3.18 pull from 9/24.  This one
includes those patches and a few more on top.  The additional patches are:
- Maarten's radeon fence updates
- Some additional debugging output
From the previous pull request:
- Re-enable some dpm features that were previously disabled due
  to a bug that was fixed in 3.16
- Make some arrays static
- re-arrange some audio code to properly reflect connected status
  in the audio driver

* 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/kv: add uvd/vce info to dpm debugfs output
  drm/radeon/ci: add uvd/vce info to dpm debugfs output
  drm/radeon: export reservation_object from dmabuf to ttm
  drm/radeon: cope with foreign fences inside the reservation object
  drm/radeon: cope with foreign fences inside display
  drm/radeon/cik: write gfx ucode version to ucode addr reg
  drm/radeon/si: print full CS when we hit a packet 0
  drm/radeon: remove unecessary includes
  drm/radeon/combios: declare legacy_connector_convert as static
  drm/radeon/atombios: declare connector convert tables as static
  drm/radeon: drop btc_get_max_clock_from_voltage_dependency_table
  drm/radeon/dpm: drop clk/voltage dependency filters for BTC
  drm/radeon/dpm: drop clk/voltage dependency filters for CI
  drm/radeon/dpm: drop clk/voltage dependency filters for SI
  drm/radeon/dpm: drop clk/voltage dependency filters for NI
  drm/radeon: disable audio when we disable hdmi (v2)
  drm/radeon: split audio enable between eg and r600 (v2)
  drm/radeon: consolidate r600_audio.c into r600_hdmi.c
  drm/radeon: consolidate duplicate encode is digital function
  drm/radeon: fix register name to match internal name
parents 7a42e83d 369283bf

drivers/gpu/drm/radeon/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 
	radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \

	rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \

	r200.o radeon_legacy_tv.o r600_cs.o r600_blit_shaders.o \

	radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o dce3_1_afmt.o \

	radeon_pm.o atombios_dp.o r600_hdmi.o dce3_1_afmt.o \

	evergreen.o evergreen_cs.o evergreen_blit_shaders.o \

	evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \

	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \

drivers/gpu/drm/radeon/atombios_encoders.c

+0 −23
Original line number Diff line number Diff line
@@ -291,29 +291,6 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *encoder) 
bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,

				struct drm_display_mode *mode);





static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)

{

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	switch (radeon_encoder->encoder_id) {

	case ENCODER_OBJECT_ID_INTERNAL_LVDS:

	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:

	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:

	case ENCODER_OBJECT_ID_INTERNAL_DVO1:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:

	case ENCODER_OBJECT_ID_INTERNAL_DDI:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:

	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:

	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:

		return true;

	default:

		return false;

	}

}



static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,

				   const struct drm_display_mode *mode,

				   struct drm_display_mode *adjusted_mode)

drivers/gpu/drm/radeon/btc_dpm.c

+0 −51
Original line number Diff line number Diff line
@@ -1170,23 +1170,6 @@ static const struct radeon_blacklist_clocks btc_blacklist_clocks[] = 
        { 25000, 30000, RADEON_SCLK_UP }

};



void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

						     u32 *max_clock)

{

	u32 i, clock = 0;



	if ((table == NULL) || (table->count == 0)) {

		*max_clock = clock;

		return;

	}



	for (i = 0; i < table->count; i++) {

		if (clock < table->entries[i].clk)

			clock = table->entries[i].clk;

	}

	*max_clock = clock;

}



void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

					u32 clock, u16 max_voltage, u16 *voltage)

{
@@ -2099,7 +2082,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
	bool disable_mclk_switching;

	u32 mclk, sclk;

	u16 vddc, vddci;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;



	if ((rdev->pm.dpm.new_active_crtc_count > 1) ||

	    btc_dpm_vblank_too_short(rdev))
@@ -2141,39 +2123,6 @@ static void btc_apply_state_adjust_rules(struct radeon_device *rdev, 
			ps->low.vddci = max_limits->vddci;

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	if (max_sclk_vddc) {

		if (ps->low.sclk > max_sclk_vddc)

			ps->low.sclk = max_sclk_vddc;

		if (ps->medium.sclk > max_sclk_vddc)

			ps->medium.sclk = max_sclk_vddc;

		if (ps->high.sclk > max_sclk_vddc)

			ps->high.sclk = max_sclk_vddc;

	}

	if (max_mclk_vddci) {

		if (ps->low.mclk > max_mclk_vddci)

			ps->low.mclk = max_mclk_vddci;

		if (ps->medium.mclk > max_mclk_vddci)

			ps->medium.mclk = max_mclk_vddci;

		if (ps->high.mclk > max_mclk_vddci)

			ps->high.mclk = max_mclk_vddci;

	}

	if (max_mclk_vddc) {

		if (ps->low.mclk > max_mclk_vddc)

			ps->low.mclk = max_mclk_vddc;

		if (ps->medium.mclk > max_mclk_vddc)

			ps->medium.mclk = max_mclk_vddc;

		if (ps->high.mclk > max_mclk_vddc)

			ps->high.mclk = max_mclk_vddc;

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {

drivers/gpu/drm/radeon/btc_dpm.h

+0 −2
Original line number Diff line number Diff line
@@ -46,8 +46,6 @@ void btc_adjust_clock_combinations(struct radeon_device *rdev, 
				   struct rv7xx_pl *pl);

void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,

					u32 clock, u16 max_voltage, u16 *voltage);

void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

						     u32 *max_clock);

void btc_apply_voltage_delta_rules(struct radeon_device *rdev,

				   u16 max_vddc, u16 max_vddci,

				   u16 *vddc, u16 *vddci);

drivers/gpu/drm/radeon/ci_dpm.c

+4 −26
Original line number Diff line number Diff line
@@ -162,8 +162,6 @@ static const struct ci_pt_config_reg didt_config_ci[] = 
};



extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);

extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,

							    u32 *max_clock);

extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,

				       u32 arb_freq_src, u32 arb_freq_dest);

extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
@@ -748,7 +746,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 
	struct radeon_clock_and_voltage_limits *max_limits;

	bool disable_mclk_switching;

	u32 sclk, mclk;

	u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;

	int i;



	if (rps->vce_active) {
@@ -784,29 +781,6 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev, 
		}

	}



	/* limit clocks to max supported clocks based on voltage dependency tables */

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,

							&max_sclk_vddc);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,

							&max_mclk_vddci);

	btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,

							&max_mclk_vddc);



	for (i = 0; i < ps->performance_level_count; i++) {

		if (max_sclk_vddc) {

			if (ps->performance_levels[i].sclk > max_sclk_vddc)

				ps->performance_levels[i].sclk = max_sclk_vddc;

		}

		if (max_mclk_vddci) {

			if (ps->performance_levels[i].mclk > max_mclk_vddci)

				ps->performance_levels[i].mclk = max_mclk_vddci;

		}

		if (max_mclk_vddc) {

			if (ps->performance_levels[i].mclk > max_mclk_vddc)

				ps->performance_levels[i].mclk = max_mclk_vddc;

		}

	}



	/* XXX validate the min clocks required for display */



	if (disable_mclk_switching) {
@@ -5293,9 +5267,13 @@ int ci_dpm_init(struct radeon_device *rdev) 
void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,

						    struct seq_file *m)

{

	struct ci_power_info *pi = ci_get_pi(rdev);

	struct radeon_ps *rps = &pi->current_rps;

	u32 sclk = ci_get_average_sclk_freq(rdev);

	u32 mclk = ci_get_average_mclk_freq(rdev);



	seq_printf(m, "uvd    %sabled\n", pi->uvd_enabled ? "en" : "dis");

	seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");

	seq_printf(m, "power level avg    sclk: %u mclk: %u\n",

		   sclk, mclk);

}