Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit cc55b1f5 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files

drm/amd/display: Set mpcc_disconnect_pending during MPC reset 



This prevents an issue where the MPCC will not go to idle due to us not
waiting for it to become idle during disable plane.

Signed-off-by: default avatarAndrew Jiang <Andrew.Jiang@amd.com>
Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 16a29dd3

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

+14 −4
Original line number Diff line number Diff line
@@ -42,15 +42,25 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) 
{

	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

	uint32_t blank_en = blank ? 1 : 0;

	uint32_t reg_val = 0;



	REG_UPDATE_2(DCHUBP_CNTL,

	reg_val = REG_UPDATE_2(DCHUBP_CNTL,

			HUBP_BLANK_EN, blank_en,

			HUBP_TTU_DISABLE, blank_en);



	if (blank) {

		if (reg_val) {

			/* init sequence workaround: in case HUBP is

			 * power gated, this wait would timeout.

			 *

			 * we just wrote reg_val to non-0, if it stay 0

			 * it means HUBP is gated

			 */

			REG_WAIT(DCHUBP_CNTL,

					HUBP_NO_OUTSTANDING_REQ, 1,

					1, 200);

		}



		hubp->mpcc_id = 0xf;

		hubp->opp_id = 0xf;

	}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+2 −2
Original line number Diff line number Diff line
@@ -782,8 +782,8 @@ static void dcn10_init_hw(struct dc *dc) 
		hubp->opp_id = 0xf;

		hubp->power_gated = false;



		if (hubp->opp_id != 0xf)

			pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id];

		dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;

		pipe_ctx->stream_res.opp = dc->res_pool->opps[i];



		plane_atomic_disconnect(dc, pipe_ctx);

	}