Loading drivers/clk/qcom/camcc-lito.c +17 −2 Original line number Original line Diff line number Diff line Loading @@ -64,7 +64,7 @@ static const char * const cam_cc_parent_names_0[] = { }; }; static const struct parent_map cam_cc_parent_map_1[] = { static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO_MX, 0 }, { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_AUX, 5 }, { P_CAM_CC_PLL2_OUT_AUX, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; }; Loading Loading @@ -588,6 +588,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .name = "cam_cc_cci_0_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -607,6 +608,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .name = "cam_cc_cci_1_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -634,6 +636,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_2, .parent_names = cam_cc_parent_names_2, Loading Loading @@ -661,6 +664,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -680,6 +684,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -699,6 +704,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -718,6 +724,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -747,6 +754,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -955,6 +963,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .name = "cam_cc_ife_lite_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1082,7 +1091,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { }; }; static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { F(19200000, P_BI_TCXO_MX, 1, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), F(24000000, P_CAM_CC_PLL2_OUT_AUX, 1, 1, 20), F(24000000, P_CAM_CC_PLL2_OUT_AUX, 1, 1, 20), F(34285714, P_CAM_CC_PLL2_OUT_AUX, 14, 0, 0), F(34285714, P_CAM_CC_PLL2_OUT_AUX, 14, 0, 0), { } { } Loading @@ -1094,6 +1103,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1113,6 +1123,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1132,6 +1143,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1151,6 +1163,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1170,6 +1183,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .name = "cam_cc_mclk4_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading Loading @@ -1220,6 +1234,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .parent_map = cam_cc_parent_map_8, .parent_map = cam_cc_parent_map_8, .enable_safe_config = true, .enable_safe_config = true, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .name = "cam_cc_slow_ahb_clk_src", .parent_names = cam_cc_parent_names_8, .parent_names = cam_cc_parent_names_8, Loading drivers/clk/qcom/dispcc-lito.c +11 −0 Original line number Original line Diff line number Diff line Loading @@ -253,6 +253,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .mnd_width = 0, .mnd_width = 0, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .name = "disp_cc_mdss_byte0_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading @@ -273,6 +274,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .mnd_width = 0, .mnd_width = 0, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk_src", .name = "disp_cc_mdss_byte1_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading Loading @@ -326,6 +328,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading Loading @@ -355,6 +358,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .name = "disp_cc_mdss_dp_link_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -375,6 +379,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { .mnd_width = 16, .mnd_width = 16, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel1_clk_src", .name = "disp_cc_mdss_dp_pixel1_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -394,6 +399,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .mnd_width = 16, .mnd_width = 16, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -414,6 +420,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .name = "disp_cc_mdss_esc0_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading @@ -432,6 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk_src", .name = "disp_cc_mdss_esc1_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading Loading @@ -480,6 +488,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .mnd_width = 8, .mnd_width = 8, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .name = "disp_cc_mdss_pclk0_clk_src", .parent_names = disp_cc_parent_names_4, .parent_names = disp_cc_parent_names_4, Loading @@ -500,6 +509,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .mnd_width = 8, .mnd_width = 8, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk_src", .name = "disp_cc_mdss_pclk1_clk_src", .parent_names = disp_cc_parent_names_4, .parent_names = disp_cc_parent_names_4, Loading Loading @@ -544,6 +554,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .name = "disp_cc_mdss_vsync_clk_src", .parent_names = disp_cc_parent_names_2, .parent_names = disp_cc_parent_names_2, Loading drivers/clk/qcom/gpucc-lito.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -128,6 +128,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = gpu_cc_parent_map_0, .parent_map = gpu_cc_parent_map_0, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .name = "gpu_cc_gmu_clk_src", .parent_names = gpu_cc_parent_names_0, .parent_names = gpu_cc_parent_names_0, Loading @@ -154,6 +155,7 @@ static struct clk_rcg2 gpu_cc_rbcpr_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = gpu_cc_parent_map_1, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_rbcpr_clk_src, .freq_tbl = ftbl_gpu_cc_rbcpr_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_rbcpr_clk_src", .name = "gpu_cc_rbcpr_clk_src", .parent_names = gpu_cc_parent_names_1, .parent_names = gpu_cc_parent_names_1, Loading drivers/clk/qcom/npucc-lito.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -363,6 +363,7 @@ static struct clk_rcg2 npu_cc_lmh_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = npu_cc_parent_map_0, .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_lmh_clk_src", .name = "npu_cc_lmh_clk_src", .parent_names = npu_cc_parent_names_0, .parent_names = npu_cc_parent_names_0, Loading Loading @@ -415,6 +416,7 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = npu_cc_parent_map_2, .parent_map = npu_cc_parent_map_2, .freq_tbl = ftbl_npu_dsp_core_clk_src, .freq_tbl = ftbl_npu_dsp_core_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "npu_dsp_core_clk_src", .name = "npu_dsp_core_clk_src", .parent_names = npu_cc_parent_names_2, .parent_names = npu_cc_parent_names_2, Loading Loading
drivers/clk/qcom/camcc-lito.c +17 −2 Original line number Original line Diff line number Diff line Loading @@ -64,7 +64,7 @@ static const char * const cam_cc_parent_names_0[] = { }; }; static const struct parent_map cam_cc_parent_map_1[] = { static const struct parent_map cam_cc_parent_map_1[] = { { P_BI_TCXO_MX, 0 }, { P_BI_TCXO, 0 }, { P_CAM_CC_PLL2_OUT_AUX, 5 }, { P_CAM_CC_PLL2_OUT_AUX, 5 }, { P_CORE_BI_PLL_TEST_SE, 7 }, { P_CORE_BI_PLL_TEST_SE, 7 }, }; }; Loading Loading @@ -588,6 +588,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_0_clk_src", .name = "cam_cc_cci_0_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -607,6 +608,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .freq_tbl = ftbl_cam_cc_cci_0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cci_1_clk_src", .name = "cam_cc_cci_1_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -634,6 +636,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_2, .parent_map = cam_cc_parent_map_2, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_cphy_rx_clk_src", .name = "cam_cc_cphy_rx_clk_src", .parent_names = cam_cc_parent_names_2, .parent_names = cam_cc_parent_names_2, Loading Loading @@ -661,6 +664,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi0phytimer_clk_src", .name = "cam_cc_csi0phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -680,6 +684,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi1phytimer_clk_src", .name = "cam_cc_csi1phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -699,6 +704,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi2phytimer_clk_src", .name = "cam_cc_csi2phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading @@ -718,6 +724,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_csi3phytimer_clk_src", .name = "cam_cc_csi3phytimer_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -747,6 +754,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .freq_tbl = ftbl_cam_cc_fast_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_fast_ahb_clk_src", .name = "cam_cc_fast_ahb_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -955,6 +963,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_0, .parent_map = cam_cc_parent_map_0, .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, .freq_tbl = ftbl_cam_cc_ife_lite_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_ife_lite_clk_src", .name = "cam_cc_ife_lite_clk_src", .parent_names = cam_cc_parent_names_0, .parent_names = cam_cc_parent_names_0, Loading Loading @@ -1082,7 +1091,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = { }; }; static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = { F(19200000, P_BI_TCXO_MX, 1, 0, 0), F(19200000, P_BI_TCXO, 1, 0, 0), F(24000000, P_CAM_CC_PLL2_OUT_AUX, 1, 1, 20), F(24000000, P_CAM_CC_PLL2_OUT_AUX, 1, 1, 20), F(34285714, P_CAM_CC_PLL2_OUT_AUX, 14, 0, 0), F(34285714, P_CAM_CC_PLL2_OUT_AUX, 14, 0, 0), { } { } Loading @@ -1094,6 +1103,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk0_clk_src", .name = "cam_cc_mclk0_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1113,6 +1123,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk1_clk_src", .name = "cam_cc_mclk1_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1132,6 +1143,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk2_clk_src", .name = "cam_cc_mclk2_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1151,6 +1163,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk3_clk_src", .name = "cam_cc_mclk3_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading @@ -1170,6 +1183,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = cam_cc_parent_map_1, .parent_map = cam_cc_parent_map_1, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .freq_tbl = ftbl_cam_cc_mclk0_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_mclk4_clk_src", .name = "cam_cc_mclk4_clk_src", .parent_names = cam_cc_parent_names_1, .parent_names = cam_cc_parent_names_1, Loading Loading @@ -1220,6 +1234,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { .parent_map = cam_cc_parent_map_8, .parent_map = cam_cc_parent_map_8, .enable_safe_config = true, .enable_safe_config = true, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .freq_tbl = ftbl_cam_cc_slow_ahb_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "cam_cc_slow_ahb_clk_src", .name = "cam_cc_slow_ahb_clk_src", .parent_names = cam_cc_parent_names_8, .parent_names = cam_cc_parent_names_8, Loading
drivers/clk/qcom/dispcc-lito.c +11 −0 Original line number Original line Diff line number Diff line Loading @@ -253,6 +253,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .mnd_width = 0, .mnd_width = 0, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte0_clk_src", .name = "disp_cc_mdss_byte0_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading @@ -273,6 +274,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .mnd_width = 0, .mnd_width = 0, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_byte1_clk_src", .name = "disp_cc_mdss_byte1_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading Loading @@ -326,6 +328,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_crypto_clk_src", .name = "disp_cc_mdss_dp_crypto_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading Loading @@ -355,6 +358,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .name = "disp_cc_mdss_dp_link_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -375,6 +379,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { .mnd_width = 16, .mnd_width = 16, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel1_clk_src", .name = "disp_cc_mdss_dp_pixel1_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -394,6 +399,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { .mnd_width = 16, .mnd_width = 16, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_1, .parent_map = disp_cc_parent_map_1, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_pixel_clk_src", .name = "disp_cc_mdss_dp_pixel_clk_src", .parent_names = disp_cc_parent_names_1, .parent_names = disp_cc_parent_names_1, Loading @@ -414,6 +420,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc0_clk_src", .name = "disp_cc_mdss_esc0_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading @@ -432,6 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_0, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_esc1_clk_src", .name = "disp_cc_mdss_esc1_clk_src", .parent_names = disp_cc_parent_names_0, .parent_names = disp_cc_parent_names_0, Loading Loading @@ -480,6 +488,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .mnd_width = 8, .mnd_width = 8, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk0_clk_src", .name = "disp_cc_mdss_pclk0_clk_src", .parent_names = disp_cc_parent_names_4, .parent_names = disp_cc_parent_names_4, Loading @@ -500,6 +509,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .mnd_width = 8, .mnd_width = 8, .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_4, .parent_map = disp_cc_parent_map_4, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_pclk1_clk_src", .name = "disp_cc_mdss_pclk1_clk_src", .parent_names = disp_cc_parent_names_4, .parent_names = disp_cc_parent_names_4, Loading Loading @@ -544,6 +554,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = disp_cc_parent_map_2, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_vsync_clk_src", .name = "disp_cc_mdss_vsync_clk_src", .parent_names = disp_cc_parent_names_2, .parent_names = disp_cc_parent_names_2, Loading
drivers/clk/qcom/gpucc-lito.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -128,6 +128,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = gpu_cc_parent_map_0, .parent_map = gpu_cc_parent_map_0, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .freq_tbl = ftbl_gpu_cc_gmu_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_gmu_clk_src", .name = "gpu_cc_gmu_clk_src", .parent_names = gpu_cc_parent_names_0, .parent_names = gpu_cc_parent_names_0, Loading @@ -154,6 +155,7 @@ static struct clk_rcg2 gpu_cc_rbcpr_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = gpu_cc_parent_map_1, .parent_map = gpu_cc_parent_map_1, .freq_tbl = ftbl_gpu_cc_rbcpr_clk_src, .freq_tbl = ftbl_gpu_cc_rbcpr_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "gpu_cc_rbcpr_clk_src", .name = "gpu_cc_rbcpr_clk_src", .parent_names = gpu_cc_parent_names_1, .parent_names = gpu_cc_parent_names_1, Loading
drivers/clk/qcom/npucc-lito.c +2 −0 Original line number Original line Diff line number Diff line Loading @@ -363,6 +363,7 @@ static struct clk_rcg2 npu_cc_lmh_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = npu_cc_parent_map_0, .parent_map = npu_cc_parent_map_0, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .freq_tbl = ftbl_npu_cc_lmh_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "npu_cc_lmh_clk_src", .name = "npu_cc_lmh_clk_src", .parent_names = npu_cc_parent_names_0, .parent_names = npu_cc_parent_names_0, Loading Loading @@ -415,6 +416,7 @@ static struct clk_rcg2 npu_dsp_core_clk_src = { .hid_width = 5, .hid_width = 5, .parent_map = npu_cc_parent_map_2, .parent_map = npu_cc_parent_map_2, .freq_tbl = ftbl_npu_dsp_core_clk_src, .freq_tbl = ftbl_npu_dsp_core_clk_src, .enable_safe_config = true, .clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){ .name = "npu_dsp_core_clk_src", .name = "npu_dsp_core_clk_src", .parent_names = npu_cc_parent_names_2, .parent_names = npu_cc_parent_names_2, Loading
