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Commit cbd54fe0 authored by Robert Nelson's avatar Robert Nelson Committed by Shawn Guo
Browse files

ARM: dts: imx6dl-udoo: Add board support based off imx6q-udoo 

For more information about the Udoo boards:
http://www.udoo.org/



Signed-off-by: default avatarRobert Nelson <robertcnelson@gmail.com>
Reviewed-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 99fc5ba0

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -234,6 +234,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ 
	imx6dl-tx6dl-comtft.dtb \

	imx6dl-tx6u-801x.dtb \

	imx6dl-tx6u-811x.dtb \

	imx6dl-udoo.dtb \

	imx6dl-wandboard.dtb \

	imx6dl-wandboard-revb1.dtb \

	imx6q-arm2.dtb \

arch/arm/boot/dts/imx6dl-udoo.dts

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/*

 * Copyright 2013 Freescale Semiconductor, Inc.

 *

 * Author: Fabio Estevam <fabio.estevam@freescale.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */

/dts-v1/;

#include "imx6dl.dtsi"

#include "imx6qdl-udoo.dtsi"



/ {

	model = "Udoo i.MX6 Dual-lite Board";

	compatible = "udoo,imx6dl-udoo", "fsl,imx6dl";

};

arch/arm/boot/dts/imx6q-udoo.dts

+1 −123
Original line number Diff line number Diff line
@@ -8,137 +8,15 @@ 
 * published by the Free Software Foundation.

 *

 */



/dts-v1/;

#include "imx6q.dtsi"

#include "imx6qdl-udoo.dtsi"



/ {

	model = "Udoo i.MX6 Quad Board";

	compatible = "udoo,imx6q-udoo", "fsl,imx6q";



	chosen {

		stdout-path = &uart2;

	};



	memory {

		reg = <0x10000000 0x40000000>;

	};



	regulators {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		reg_usb_h1_vbus: regulator@0 {

			compatible = "regulator-fixed";

			reg = <0>;

			regulator-name = "usb_h1_vbus";

			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;

			enable-active-high;

			startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */

			gpio = <&gpio7 12 0>;

		};

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	status = "okay";

};



&hdmi {

	ddc-i2c-bus = <&i2c2>;

	status = "okay";

};



&i2c2 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c2>;

	status = "okay";

};



&iomuxc {

	imx6q-udoo {

		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8

			>;

		};



		pinctrl_i2c2: i2c2grp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1

				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1

			>;

		};



		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usbh: usbhgrp {

			fsl,pins = <

				MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000

				MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};

	};

};



&sata {

	status = "okay";

};
 


&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



&usbh1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbh>;

	vbus-supply = <&reg_usb_h1_vbus>;

	clocks = <&clks 201>;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3>;

	non-removable;

	status = "okay";

};

arch/arm/boot/dts/imx6qdl-udoo.dtsi

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Original line number Diff line number Diff line 
/*

 * Copyright 2013 Freescale Semiconductor, Inc.

 *

 * Author: Fabio Estevam <fabio.estevam@freescale.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 */



/ {

	chosen {

		stdout-path = &uart2;

	};



	memory {

		reg = <0x10000000 0x40000000>;

	};



	regulators {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		reg_usb_h1_vbus: regulator@0 {

			compatible = "regulator-fixed";

			reg = <0>;

			regulator-name = "usb_h1_vbus";

			regulator-min-microvolt = <5000000>;

			regulator-max-microvolt = <5000000>;

			enable-active-high;

			startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */

			gpio = <&gpio7 12 0>;

		};

	};

};



&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet>;

	phy-mode = "rgmii";

	status = "okay";

};



&hdmi {

	ddc-i2c-bus = <&i2c2>;

	status = "okay";

};



&i2c2 {

	clock-frequency = <100000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_i2c2>;

	status = "okay";

};



&iomuxc {

	imx6q-udoo {

		pinctrl_enet: enetgrp {

			fsl,pins = <

				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0

				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0

				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0

				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0

				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0

				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0

				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0

				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0

				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0

				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0

				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0

				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0

				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0

				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8

			>;

		};



		pinctrl_i2c2: i2c2grp {

			fsl,pins = <

				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1

				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1

			>;

		};



		pinctrl_uart2: uart2grp {

			fsl,pins = <

				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1

				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1

			>;

		};



		pinctrl_usbh: usbhgrp {

			fsl,pins = <

				MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000

				MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0

			>;

		};



		pinctrl_usdhc3: usdhc3grp {

			fsl,pins = <

				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059

				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059

				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059

				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059

				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059

				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059

			>;

		};

	};

};



&uart2 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart2>;

	status = "okay";

};



&usbh1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usbh>;

	vbus-supply = <&reg_usb_h1_vbus>;

	clocks = <&clks 201>;

	status = "okay";

};



&usdhc3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_usdhc3>;

	non-removable;

	status = "okay";

};