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Commit cba3574f authored by Will Deacon's avatar Will Deacon
Browse files

arm64: move update_mmu_cache() into asm/pgtable.h 



Mark Brown reported an allnoconfig build failure in -next:

  Today's linux-next fails to build an arm64 allnoconfig due to "mm:
  make GUP handle pfn mapping unless FOLL_GET is requested" which
  causes:

  >       arm64-allnoconfig
  > ../mm/gup.c:51:4: error: implicit declaration of function
    'update_mmu_cache' [-Werror=implicit-function-declaration]

Fix the error by moving the function to asm/pgtable.h, as is the case
for most other architectures.

Reported-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent aaf6f2f0

arch/arm64/include/asm/pgtable.h

+15 −0
Original line number Original line Diff line number Diff line
@@ -505,6 +505,21 @@ extern int kern_addr_valid(unsigned long addr); 




#define pgtable_cache_init() do { } while (0)

#define pgtable_cache_init() do { } while (0)





/*

 * On AArch64, the cache coherency is handled via the set_pte_at() function.

 */

static inline void update_mmu_cache(struct vm_area_struct *vma,

				    unsigned long addr, pte_t *ptep)

{

	/*

	 * set_pte() does not have a DSB for user mappings, so make sure that

	 * the page table write is visible.

	 */

	dsb(ishst);

}



#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)



#endif /* !__ASSEMBLY__ */

#endif /* !__ASSEMBLY__ */





#endif /* __ASM_PGTABLE_H */
 
#endif /* __ASM_PGTABLE_H */

arch/arm64/include/asm/tlbflush.h

+0 −14
Original line number Original line Diff line number Diff line
@@ -154,20 +154,6 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, 
	asm("tlbi	vae1is, %0" : : "r" (addr));

	asm("tlbi	vae1is, %0" : : "r" (addr));

	dsb(ish);

	dsb(ish);

}

}

/*

 * On AArch64, the cache coherency is handled via the set_pte_at() function.

 */

static inline void update_mmu_cache(struct vm_area_struct *vma,

				    unsigned long addr, pte_t *ptep)

{

	/*

	 * set_pte() does not have a DSB for user mappings, so make sure that

	 * the page table write is visible.

	 */

	dsb(ishst);

}



#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)





#endif

#endif