Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ca85430a authored by Mukesh Kumar Savaliya's avatar Mukesh Kumar Savaliya
Browse files

serial: msm_geni_serial: Ensure to set clock freq correctly 



This patch enables UART clock to run at half the rate and make
sure write to register gets executed with read back of the same
regiter.

Change-Id: I4568ec8fb471cd24eee27bc4cc3bd76e27ea68d8
Signed-off-by: default avatarMukesh Kumar Savaliya <msavaliy@codeaurora.org>
parent 37d31a68

drivers/tty/serial/msm_geni_serial.c

+14 −16
Original line number Diff line number Diff line
@@ -160,7 +160,6 @@ struct msm_geni_serial_port { 
	int ioctl_count;

	int edge_count;

	bool manual_flow;

	bool sampling_rate;

};



static const struct uart_ops msm_geni_serial_pops;
@@ -1769,8 +1768,6 @@ static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback, 
		u32 rx_parity_cfg, u32 bits_per_char, u32 stop_bit_len,

		u32 s_clk_cfg)

{

	struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);



	geni_write_reg_nolog(loopback, uport->membase, SE_UART_LOOPBACK_CFG);

	geni_write_reg_nolog(tx_trans_cfg, uport->membase,

							SE_UART_TX_TRANS_CFG);
@@ -1788,7 +1785,7 @@ static void geni_serial_write_term_regs(struct uart_port *uport, u32 loopback, 
						SE_UART_TX_STOP_BIT_LEN);

	geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(s_clk_cfg, uport->membase, GENI_SER_S_CLK_CFG);

	if (msm_port->sampling_rate)



	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);

}
@@ -1810,6 +1807,9 @@ static int get_clk_div_rate(unsigned int baud, unsigned long *desired_clk_rate) 
	clk_div = ser_clk / *desired_clk_rate;

	*desired_clk_rate = ser_clk;

exit_get_clk_div_rate:

	if (clk_div)

		clk_div = clk_div*2;



	return clk_div;

}
@@ -1829,7 +1829,8 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	unsigned long clk_rate;

	unsigned long flags;



	if (port->sampling_rate)

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	if (!uart_console(uport)) {
@@ -1856,8 +1857,6 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	if (clk_div <= 0)

		goto exit_set_termios;



	if (port->sampling_rate)

		clk_div = clk_div*2;

	uport->uartclk = clk_rate;

	clk_set_rate(port->serial_rsc.se_clk, clk_rate);

	ser_clk_cfg |= SER_CLK_EN;
@@ -2125,7 +2124,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
		goto exit_geni_serial_earlyconsetup;

	}



	clk_div = clk_div*2;

	s_clk_cfg |= SER_CLK_EN;

	s_clk_cfg |= (clk_div << CLK_DIV_SHFT);
@@ -2135,6 +2133,9 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
	 */

	msm_geni_serial_poll_cancel_tx(uport);

	msm_geni_serial_abort_rx(uport);



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	se_get_packing_config(8, 1, false, &cfg0, &cfg1);
@@ -2378,10 +2379,6 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 


	uport->dev = &pdev->dev;



	dev_port->sampling_rate =

		of_property_read_bool(pdev->dev.of_node,

				"qcom,change-sampling-rate");



	wrapper_ph_node = of_parse_phandle(pdev->dev.of_node,

					"qcom,wrapper-core", 0);

	if (IS_ERR_OR_NULL(wrapper_ph_node)) {
@@ -2522,7 +2519,8 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		pm_runtime_enable(&pdev->dev);

	}



	if (dev_port->sampling_rate)

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",