Loading msm/dsi/dsi_ctrl.c +25 −14 Original line number Diff line number Diff line Loading @@ -1273,9 +1273,7 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl, if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) { dsi_ctrl_wait_for_video_done(dsi_ctrl); if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); dsi_ctrl_mask_overflow(dsi_ctrl, true); atomic_set(&dsi_ctrl->dma_irq_trig, 0); dsi_ctrl_enable_status_interrupt(dsi_ctrl, Loading Loading @@ -1308,9 +1306,8 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl, dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait); } if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); dsi_ctrl_mask_overflow(dsi_ctrl, false); dsi_hw_ops.reset_cmd_fifo(&dsi_ctrl->hw); /* Loading Loading @@ -3213,6 +3210,28 @@ int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl, return rc; } /** * dsi_ctrl_mask_overflow() - API to mask/unmask overflow error. * @dsi_ctrl: DSI controller handle. * @enable: variable to control masking/unmasking. */ void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable) { struct dsi_ctrl_hw_ops dsi_hw_ops; dsi_hw_ops = dsi_ctrl->hw.ops; if (enable) { if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); } else { if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); } } /** * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command. * @dsi_ctrl: DSI controller handle. Loading Loading @@ -3245,9 +3264,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) if ((flags & DSI_CTRL_CMD_BROADCAST) && (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) { dsi_ctrl_wait_for_video_done(dsi_ctrl); if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); atomic_set(&dsi_ctrl->dma_irq_trig, 0); dsi_ctrl_enable_status_interrupt(dsi_ctrl, DSI_SINT_CMD_MODE_DMA_DONE, NULL); Loading @@ -3264,11 +3280,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait); } if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) { if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4) dsi_hw_ops.soft_reset(&dsi_ctrl->hw); Loading msm/dsi/dsi_ctrl.h +7 −0 Original line number Diff line number Diff line Loading @@ -861,4 +861,11 @@ void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable); * @dsi_ctrl: DSI controller handle. */ int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl); /** * dsi_ctrl_mask_overflow() - API to mask/unmask overflow errors. * @dsi_ctrl: DSI controller handle. * @enable: variable to control masking/unmasking. */ void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable); #endif /* _DSI_CTRL_H_ */ msm/dsi/dsi_display.c +19 −0 Original line number Diff line number Diff line Loading @@ -2721,6 +2721,23 @@ static int dsi_display_wake_up(struct dsi_display *display) return 0; } static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags, bool enable) { struct dsi_display_ctrl *ctrl; int i; if (!(flags & DSI_CTRL_CMD_LAST_COMMAND)) return; display_for_each_ctrl(i, display) { ctrl = &display->ctrl[i]; if (!ctrl) continue; dsi_ctrl_mask_overflow(ctrl->ctrl, enable); } } static int dsi_display_broadcast_cmd(struct dsi_display *display, const struct mipi_dsi_msg *msg) { Loading Loading @@ -2750,6 +2767,7 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, * 2. Trigger commands */ m_ctrl = &display->ctrl[display->cmd_master_idx]; dsi_display_mask_overflow(display, m_flags, true); rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags); if (rc) { DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n", Loading Loading @@ -2785,6 +2803,7 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, } error: dsi_display_mask_overflow(display, m_flags, false); return rc; } Loading Loading
msm/dsi/dsi_ctrl.c +25 −14 Original line number Diff line number Diff line Loading @@ -1273,9 +1273,7 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl, if (!(flags & DSI_CTRL_CMD_DEFER_TRIGGER)) { dsi_ctrl_wait_for_video_done(dsi_ctrl); if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); dsi_ctrl_mask_overflow(dsi_ctrl, true); atomic_set(&dsi_ctrl->dma_irq_trig, 0); dsi_ctrl_enable_status_interrupt(dsi_ctrl, Loading Loading @@ -1308,9 +1306,8 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl, dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait); } if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); dsi_ctrl_mask_overflow(dsi_ctrl, false); dsi_hw_ops.reset_cmd_fifo(&dsi_ctrl->hw); /* Loading Loading @@ -3213,6 +3210,28 @@ int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl, return rc; } /** * dsi_ctrl_mask_overflow() - API to mask/unmask overflow error. * @dsi_ctrl: DSI controller handle. * @enable: variable to control masking/unmasking. */ void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable) { struct dsi_ctrl_hw_ops dsi_hw_ops; dsi_hw_ops = dsi_ctrl->hw.ops; if (enable) { if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); } else { if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); } } /** * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command. * @dsi_ctrl: DSI controller handle. Loading Loading @@ -3245,9 +3264,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) if ((flags & DSI_CTRL_CMD_BROADCAST) && (flags & DSI_CTRL_CMD_BROADCAST_MASTER)) { dsi_ctrl_wait_for_video_done(dsi_ctrl); if (dsi_hw_ops.mask_error_intr) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), true); atomic_set(&dsi_ctrl->dma_irq_trig, 0); dsi_ctrl_enable_status_interrupt(dsi_ctrl, DSI_SINT_CMD_MODE_DMA_DONE, NULL); Loading @@ -3264,11 +3280,6 @@ int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags) dsi_ctrl_dma_cmd_wait_for_done(&dsi_ctrl->dma_cmd_wait); } if (dsi_hw_ops.mask_error_intr && !dsi_ctrl->esd_check_underway) dsi_hw_ops.mask_error_intr(&dsi_ctrl->hw, BIT(DSI_FIFO_OVERFLOW), false); if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) { if (dsi_ctrl->version < DSI_CTRL_VERSION_2_4) dsi_hw_ops.soft_reset(&dsi_ctrl->hw); Loading
msm/dsi/dsi_ctrl.h +7 −0 Original line number Diff line number Diff line Loading @@ -861,4 +861,11 @@ void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable); * @dsi_ctrl: DSI controller handle. */ int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl); /** * dsi_ctrl_mask_overflow() - API to mask/unmask overflow errors. * @dsi_ctrl: DSI controller handle. * @enable: variable to control masking/unmasking. */ void dsi_ctrl_mask_overflow(struct dsi_ctrl *dsi_ctrl, bool enable); #endif /* _DSI_CTRL_H_ */
msm/dsi/dsi_display.c +19 −0 Original line number Diff line number Diff line Loading @@ -2721,6 +2721,23 @@ static int dsi_display_wake_up(struct dsi_display *display) return 0; } static void dsi_display_mask_overflow(struct dsi_display *display, u32 flags, bool enable) { struct dsi_display_ctrl *ctrl; int i; if (!(flags & DSI_CTRL_CMD_LAST_COMMAND)) return; display_for_each_ctrl(i, display) { ctrl = &display->ctrl[i]; if (!ctrl) continue; dsi_ctrl_mask_overflow(ctrl->ctrl, enable); } } static int dsi_display_broadcast_cmd(struct dsi_display *display, const struct mipi_dsi_msg *msg) { Loading Loading @@ -2750,6 +2767,7 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, * 2. Trigger commands */ m_ctrl = &display->ctrl[display->cmd_master_idx]; dsi_display_mask_overflow(display, m_flags, true); rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, msg, &m_flags); if (rc) { DSI_ERR("[%s] cmd transfer failed on master,rc=%d\n", Loading Loading @@ -2785,6 +2803,7 @@ static int dsi_display_broadcast_cmd(struct dsi_display *display, } error: dsi_display_mask_overflow(display, m_flags, false); return rc; } Loading