Merge "disp: msm: dsi: commit DSI PHY timings after update" (ca2fbfd5) · Commits · e / devices / android_kernel_fairphone_FP4

msm/dsi/dsi_catalog.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -262,6 +262,7 @@ static void dsi_catalog_phy_4_0_init(struct dsi_phy_hw *phy)
		phy->ops.dyn_refresh_ops.cache_phy_timings =
		dsi_phy_hw_v4_0_cache_phy_timings;
		phy->ops.set_continuous_clk = dsi_phy_hw_v4_0_set_continuous_clk;
		phy->ops.commit_phy_timing = dsi_phy_hw_v4_0_commit_phy_timing;
		}

		/**

+2 −0

Original line number	Diff line number	Diff line
		@@ -116,6 +116,8 @@ int dsi_phy_hw_v4_0_lane_reset(struct dsi_phy_hw *phy);
		void dsi_phy_hw_v4_0_toggle_resync_fifo(struct dsi_phy_hw *phy);
		void dsi_phy_hw_v4_0_reset_clk_en_sel(struct dsi_phy_hw *phy);
		void dsi_phy_hw_v4_0_set_continuous_clk(struct dsi_phy_hw *phy, bool enable);
		void dsi_phy_hw_v4_0_commit_phy_timing(struct dsi_phy_hw *phy,
		struct dsi_phy_per_lane_cfgs *timing);

		/* DSI controller common ops */
		u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl);

+4 −1

Original line number	Diff line number	Diff line
		@@ -4419,6 +4419,7 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
		int i;
		struct dsi_display_ctrl *ctrl;
		struct dsi_display_mode_priv_info *priv_info;
		bool commit_phy_timing = false;

		priv_info = mode->priv_info;
		if (!priv_info) {
		@@ -4488,6 +4489,7 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,

		if ((mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) &&
		(display->panel->panel_mode == DSI_OP_CMD_MODE)) {
		commit_phy_timing = true;
		atomic_set(&display->clkrate_change_pending, 1);

		dsi_display_validate_dms_fps(display->panel->cur_mode, mode);
		@@ -4498,7 +4500,8 @@ static int dsi_display_set_mode_sub(struct dsi_display *display,
		ctrl = &display->ctrl[i];
		rc = dsi_phy_set_timing_params(ctrl->phy,
		priv_info->phy_timing_val,
		priv_info->phy_timing_len);
		priv_info->phy_timing_len,
		commit_phy_timing);
		if (rc)
		DSI_ERR("failed to add DSI PHY timing params\n");
		}

+7 −1

Original line number	Diff line number	Diff line
		@@ -1071,6 +1071,8 @@ int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
		* @phy: DSI PHY handle
		* @timing: array holding timing params.
		* @size: size of the array.
		* @commit: boolean to indicate if programming PHY HW registers is
		* required
		*
		* When PHY timing calculator is not implemented, this array will be used to
		* pass PHY timing information.
		@@ -1078,7 +1080,7 @@ int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
		* Return: error code.
		*/
		int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
		u32 *timing, u32 size)
		u32 *timing, u32 size, bool commit)
		{
		int rc = 0;

		@@ -1091,9 +1093,13 @@ int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,

		if (phy->hw.ops.phy_timing_val)
		rc = phy->hw.ops.phy_timing_val(&phy->cfg.timing, timing, size);

		if (!rc)
		phy->cfg.is_phy_timing_present = true;

		if (phy->hw.ops.commit_phy_timing && commit)
		phy->hw.ops.commit_phy_timing(&phy->hw, &phy->cfg.timing);

		mutex_unlock(&phy->phy_lock);
		return rc;
		}

+3 −1

Original line number	Diff line number	Diff line
		@@ -244,6 +244,8 @@ int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
		* @phy: DSI PHY handle
		* @timing: array holding timing params.
		* @size: size of the array.
		* @commit: boolean to indicate if programming PHY HW registers is
		* required
		*
		* When PHY timing calculator is not implemented, this array will be used to
		* pass PHY timing information.
		@@ -251,7 +253,7 @@ int dsi_phy_set_clk_freq(struct msm_dsi_phy *phy,
		* Return: error code.
		*/
		int dsi_phy_set_timing_params(struct msm_dsi_phy *phy,
		u32 *timing, u32 size);
		u32 *timing, u32 size, bool commit);

		/**
		* dsi_phy_lane_reset() - Reset DSI PHY lanes in case of error