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Commit ca00392c authored by Eilon Greenstein's avatar Eilon Greenstein Committed by David S. Miller
Browse files

bnx2x: Using the new FW 



The new FW improves the packets per second rate. It required a lot of change in
the FW which implies many changes in the driver to support it. It is now also
possible for the driver to use a separate MSI-X vector for Rx and Tx - this also
add some to the complicity of this change.

All things said - after this patch, practically all performance matrixes show
improvement.
Though Vladislav Zolotarov is not signed on this patch, he did most of the job
and deserves credit for that.

Signed-off-by: default avatarEilon Greenstein <eilong@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6200f090

drivers/net/bnx2x.h

+28 −17
Original line number Diff line number Diff line
@@ -142,6 +142,9 @@ struct sw_rx_bd { 
struct sw_tx_bd {

	struct sk_buff	*skb;

	u16		first_bd;

	u8		flags;

/* Set on the first BD descriptor when there is a split BD */

#define BNX2X_TSO_SPLIT_BD		(1<<0)

};



struct sw_rx_page {
@@ -149,6 +152,11 @@ struct sw_rx_page { 
	DECLARE_PCI_UNMAP_ADDR(mapping)

};



union db_prod {

	struct doorbell_set_prod data;

	u32		raw;

};





/* MC hsi */

#define BCM_PAGE_SHIFT			12
@@ -234,15 +242,14 @@ struct bnx2x_fastpath { 


	struct napi_struct	napi;



	u8			is_rx_queue;



	struct host_status_block *status_blk;

	dma_addr_t		status_blk_mapping;



	struct eth_tx_db_data	*hw_tx_prods;

	dma_addr_t		tx_prods_mapping;



	struct sw_tx_bd		*tx_buf_ring;



	struct eth_tx_bd	*tx_desc_ring;

	union eth_tx_bd_types	*tx_desc_ring;

	dma_addr_t		tx_desc_mapping;



	struct sw_rx_bd		*rx_buf_ring;	/* BDs mappings ring */
@@ -272,6 +279,8 @@ struct bnx2x_fastpath { 
	u8			cl_id;	/* eth client id */

	u8			sb_id;	/* status block number in HW */



	union db_prod		tx_db;



	u16			tx_pkt_prod;

	u16			tx_pkt_cons;

	u16			tx_bd_prod;
@@ -309,21 +318,24 @@ struct bnx2x_fastpath { 
	struct xstorm_per_client_stats old_xclient;

	struct bnx2x_eth_q_stats eth_q_stats;



	char			name[IFNAMSIZ];

	/* The size is calculated using the following:

	     sizeof name field from netdev structure +

	     4 ('-Xx-' string) +

	     4 (for the digits and to make it DWORD aligned) */

#define FP_NAME_SIZE		(sizeof(((struct net_device *)0)->name) + 8)

	char			name[FP_NAME_SIZE];

	struct bnx2x		*bp; /* parent */

};



#define bnx2x_fp(bp, nr, var)		(bp->fp[nr].var)



#define BNX2X_HAS_WORK(fp)	(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))





/* MC hsi */

#define MAX_FETCH_BD			13	/* HW max BDs per packet */

#define RX_COPY_THRESH			92



#define NUM_TX_RINGS			16

#define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))

#define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))

#define MAX_TX_DESC_CNT			(TX_DESC_CNT - 1)

#define NUM_TX_BD			(TX_DESC_CNT * NUM_TX_RINGS)

#define MAX_TX_BD			(NUM_TX_BD - 1)
@@ -395,7 +407,7 @@ struct bnx2x_fastpath { 
#define DPM_TRIGER_TYPE			0x40

#define DOORBELL(bp, cid, val) \

	do { \

		writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \

		writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \

		       DPM_TRIGER_TYPE); \

	} while (0)
@@ -902,8 +914,6 @@ struct bnx2x { 
	u16			rx_quick_cons_trip;

	u16			rx_ticks_int;

	u16			rx_ticks;

/* Maximal coalescing timeout in us */

#define BNX2X_MAX_COALESCE_TOUT		(0xf0*12)



	u32			lin_cnt;
@@ -985,19 +995,20 @@ struct bnx2x { 
};





#define BNX2X_MAX_QUEUES(bp)	(IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \

						 MAX_CONTEXT)

#define BNX2X_NUM_QUEUES(bp)	max(bp->num_rx_queues, bp->num_tx_queues)

#define is_multi(bp)		(BNX2X_NUM_QUEUES(bp) > 1)

#define BNX2X_MAX_QUEUES(bp)	(IS_E1HMF(bp) ? (MAX_CONTEXT/(2 * E1HVN_MAX)) \

					      : (MAX_CONTEXT/2))

#define BNX2X_NUM_QUEUES(bp)	(bp->num_rx_queues + bp->num_tx_queues)

#define is_multi(bp)		(BNX2X_NUM_QUEUES(bp) > 2)



#define for_each_rx_queue(bp, var) \

			for (var = 0; var < bp->num_rx_queues; var++)

#define for_each_tx_queue(bp, var) \

			for (var = 0; var < bp->num_tx_queues; var++)

			for (var = bp->num_rx_queues; \

			     var < BNX2X_NUM_QUEUES(bp); var++)

#define for_each_queue(bp, var) \

			for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)

#define for_each_nondefault_queue(bp, var) \

			for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)

			for (var = 1; var < bp->num_rx_queues; var++)





void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);

drivers/net/bnx2x_fw_defs.h

+274 −105

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x_hsi.h

+260 −101

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x_main.c

+481 −407

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/bnx2x_reg.h

+31 −29
Original line number Diff line number Diff line
@@ -370,7 +370,6 @@ 
#define CFC_REG_NUM_LCIDS_LEAVING				 0x104018

/* [RW 8] The event id for aggregated interrupt 0 */

#define CSDM_REG_AGG_INT_EVENT_0				 0xc2038

#define CSDM_REG_AGG_INT_EVENT_1				 0xc203c

#define CSDM_REG_AGG_INT_EVENT_10				 0xc2060

#define CSDM_REG_AGG_INT_EVENT_11				 0xc2064

#define CSDM_REG_AGG_INT_EVENT_12				 0xc2068
@@ -378,37 +377,27 @@ 
#define CSDM_REG_AGG_INT_EVENT_14				 0xc2070

#define CSDM_REG_AGG_INT_EVENT_15				 0xc2074

#define CSDM_REG_AGG_INT_EVENT_16				 0xc2078

#define CSDM_REG_AGG_INT_EVENT_17				 0xc207c

#define CSDM_REG_AGG_INT_EVENT_18				 0xc2080

#define CSDM_REG_AGG_INT_EVENT_19				 0xc2084

#define CSDM_REG_AGG_INT_EVENT_2				 0xc2040

#define CSDM_REG_AGG_INT_EVENT_20				 0xc2088

#define CSDM_REG_AGG_INT_EVENT_21				 0xc208c

#define CSDM_REG_AGG_INT_EVENT_22				 0xc2090

#define CSDM_REG_AGG_INT_EVENT_23				 0xc2094

#define CSDM_REG_AGG_INT_EVENT_24				 0xc2098

#define CSDM_REG_AGG_INT_EVENT_25				 0xc209c

#define CSDM_REG_AGG_INT_EVENT_26				 0xc20a0

#define CSDM_REG_AGG_INT_EVENT_27				 0xc20a4

#define CSDM_REG_AGG_INT_EVENT_28				 0xc20a8

#define CSDM_REG_AGG_INT_EVENT_29				 0xc20ac

#define CSDM_REG_AGG_INT_EVENT_3				 0xc2044

#define CSDM_REG_AGG_INT_EVENT_30				 0xc20b0

#define CSDM_REG_AGG_INT_EVENT_31				 0xc20b4

#define CSDM_REG_AGG_INT_EVENT_4				 0xc2048

/* [RW 1] The T bit for aggregated interrupt 0 */

#define CSDM_REG_AGG_INT_T_0					 0xc20b8

#define CSDM_REG_AGG_INT_T_1					 0xc20bc

#define CSDM_REG_AGG_INT_T_10					 0xc20e0

#define CSDM_REG_AGG_INT_T_11					 0xc20e4

#define CSDM_REG_AGG_INT_T_12					 0xc20e8

#define CSDM_REG_AGG_INT_T_13					 0xc20ec

#define CSDM_REG_AGG_INT_T_14					 0xc20f0

#define CSDM_REG_AGG_INT_T_15					 0xc20f4

#define CSDM_REG_AGG_INT_T_16					 0xc20f8

#define CSDM_REG_AGG_INT_T_17					 0xc20fc

#define CSDM_REG_AGG_INT_T_18					 0xc2100

#define CSDM_REG_AGG_INT_T_19					 0xc2104

#define CSDM_REG_AGG_INT_EVENT_5				 0xc204c

#define CSDM_REG_AGG_INT_EVENT_6				 0xc2050

#define CSDM_REG_AGG_INT_EVENT_7				 0xc2054

#define CSDM_REG_AGG_INT_EVENT_8				 0xc2058

#define CSDM_REG_AGG_INT_EVENT_9				 0xc205c

/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)

   or auto-mask-mode (1) */

#define CSDM_REG_AGG_INT_MODE_10				 0xc21e0

#define CSDM_REG_AGG_INT_MODE_11				 0xc21e4

#define CSDM_REG_AGG_INT_MODE_12				 0xc21e8

#define CSDM_REG_AGG_INT_MODE_13				 0xc21ec

#define CSDM_REG_AGG_INT_MODE_14				 0xc21f0

#define CSDM_REG_AGG_INT_MODE_15				 0xc21f4

#define CSDM_REG_AGG_INT_MODE_16				 0xc21f8

#define CSDM_REG_AGG_INT_MODE_6 				 0xc21d0

#define CSDM_REG_AGG_INT_MODE_7 				 0xc21d4

#define CSDM_REG_AGG_INT_MODE_8 				 0xc21d8

#define CSDM_REG_AGG_INT_MODE_9 				 0xc21dc

/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */

#define CSDM_REG_CFC_RSP_START_ADDR				 0xc2008

/* [RW 16] The maximum value of the competion counter #0 */
@@ -1421,6 +1410,8 @@ 
/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0

   only. */

#define MISC_REG_E1HMF_MODE					 0xa5f8

/* [RW 32] Debug only: spare RW register reset by core reset */

#define MISC_REG_GENERIC_CR_0					 0xa460

/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of

   these bits is written as a '1'; the corresponding SPIO bit will turn off

   it's drivers and become an input. This is the reset state of all GPIO
@@ -1729,6 +1720,7 @@ 
/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-

   tsdm enable; b2- usdm enable */

#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0			 0x16070

#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1			 0x16074

/* [RW 1] SAFC enable for port0. This register may get 1 only when

   ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same

   port */
@@ -2079,6 +2071,7 @@ 
#define PXP2_REG_PGL_ADDR_94_F0 				 0x120540

#define PXP2_REG_PGL_CONTROL0					 0x120490

#define PXP2_REG_PGL_CONTROL1					 0x120514

#define PXP2_REG_PGL_DEBUG					 0x120520

/* [RW 32] third dword data of expansion rom request. this register is

   special. reading from it provides a vector outstanding read requests. if

   a bit is zero it means that a read request on the corresponding tag did
@@ -2238,6 +2231,9 @@ 
/* [RW 8] The maximum number of blocks in Tetris Buffer that can be

   allocated for vq22 */

#define PXP2_REG_RD_MAX_BLKS_VQ22				 0x1203d0

/* [RW 8] The maximum number of blocks in Tetris Buffer that can be

   allocated for vq25 */

#define PXP2_REG_RD_MAX_BLKS_VQ25				 0x1203dc

/* [RW 8] The maximum number of blocks in Tetris Buffer that can be

   allocated for vq6 */

#define PXP2_REG_RD_MAX_BLKS_VQ6				 0x120390
@@ -3835,6 +3831,7 @@ 
#define TM_REG_LIN0_PHY_ADDR					 0x164270

/* [RW 1] Linear0 physical address valid. */

#define TM_REG_LIN0_PHY_ADDR_VALID				 0x164248

#define TM_REG_LIN0_SCAN_ON					 0x1640d0

/* [RW 24] Linear0 array scan timeout. */

#define TM_REG_LIN0_SCAN_TIME					 0x16403c

/* [RW 32] Linear1 logic address. */
@@ -4363,6 +4360,7 @@ 
#define USDM_REG_AGG_INT_EVENT_31				 0xc40b4

#define USDM_REG_AGG_INT_EVENT_4				 0xc4048

#define USDM_REG_AGG_INT_EVENT_5				 0xc404c

#define USDM_REG_AGG_INT_EVENT_6				 0xc4050

/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)

   or auto-mask-mode (1) */

#define USDM_REG_AGG_INT_MODE_0 				 0xc41b8
@@ -4379,6 +4377,10 @@ 
#define USDM_REG_AGG_INT_MODE_19				 0xc4204

#define USDM_REG_AGG_INT_MODE_4 				 0xc41c8

#define USDM_REG_AGG_INT_MODE_5 				 0xc41cc

#define USDM_REG_AGG_INT_MODE_6 				 0xc41d0

/* [RW 1] The T bit for aggregated interrupt 5 */

#define USDM_REG_AGG_INT_T_5					 0xc40cc

#define USDM_REG_AGG_INT_T_6					 0xc40d0

/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */

#define USDM_REG_CFC_RSP_START_ADDR				 0xc4008

/* [RW 16] The maximum value of the competion counter #0 */