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Commit c9f66036 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'zynqmp-soc-for-4.16' of https://github.com/Xilinx/linux-xlnx into next/drivers 

arm: Xilinx ZynqMP SoC patches for v4.16

- Create drivers/soc/xilinx folder structure
- Add ZynqMP vcu init driver

* tag 'zynqmp-soc-for-4.16' of https://github.com/Xilinx/linux-xlnx

:
  soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
  dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
  soc: xilinx: Create folder structure for soc specific drivers

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents ffdc98c4 cee8113a

Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt

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LogicoreIP designed compatible with Xilinx ZYNQ family.

-------------------------------------------------------



General concept

---------------



LogicoreIP design to provide the isolation between processing system

and programmable logic. Also provides the list of register set to configure

the frequency.



Required properties:

- compatible: shall be one of:

	"xlnx,vcu"

	"xlnx,vcu-logicoreip-1.0"

- reg, reg-names: There are two sets of registers need to provide.

	1. vcu slcr

	2. Logicore

	reg-names should contain name for the each register sequence.

- clocks: phandle for aclk and pll_ref clocksource

- clock-names: The identification string, "aclk", is always required for

   the axi clock. "pll_ref" is required for pll.

Example:



	xlnx_vcu: vcu@a0040000 {

		compatible = "xlnx,vcu-logicoreip-1.0";

		reg = <0x0 0xa0040000 0x0 0x1000>,

			 <0x0 0xa0041000 0x0 0x1000>;

		reg-names = "vcu_slcr", "logicore";

		clocks = <&si570_1>, <&clkc 71>;

		clock-names = "pll_ref", "aclk";

	};

drivers/soc/Kconfig

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@@ -16,6 +16,7 @@ source "drivers/soc/tegra/Kconfig" 
source "drivers/soc/ti/Kconfig"

source "drivers/soc/ux500/Kconfig"

source "drivers/soc/versatile/Kconfig"

source "drivers/soc/xilinx/Kconfig"

source "drivers/soc/zte/Kconfig"



endmenu

drivers/soc/Makefile

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@@ -22,4 +22,5 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ 
obj-$(CONFIG_SOC_TI)		+= ti/

obj-$(CONFIG_ARCH_U8500)	+= ux500/

obj-$(CONFIG_PLAT_VERSATILE)	+= versatile/

obj-y				+= xilinx/

obj-$(CONFIG_ARCH_ZX)		+= zte/

drivers/soc/xilinx/Kconfig

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# SPDX-License-Identifier: GPL-2.0

menu "Xilinx SoC drivers"



config XILINX_VCU

        tristate "Xilinx VCU logicoreIP Init"

        help

          Provides the driver to enable and disable the isolation between the

          processing system and programmable logic part by using the logicoreIP

          register set. This driver also configures the frequency based on the

          clock information from the logicoreIP register set.



          If you say yes here you get support for the logicoreIP.



          If unsure, say N.



          To compile this driver as a module, choose M here: the

          module will be called xlnx_vcu.



endmenu

drivers/soc/xilinx/Makefile

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# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_XILINX_VCU)	+= xlnx_vcu.o