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Commit c9ef081d authored by Yue Hin Lau's avatar Yue Hin Lau Committed by Alex Deucher
Browse files

drm/amd/display: create new structure for hubbub 



instantiating new structure hubbub in resource.c

Signed-off-by: default avatarYue Hin Lau <Yuehin.Lau@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bcb40a67

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

+52 −36
Original line number Diff line number Diff line
@@ -26,21 +26,18 @@ 
#include "dm_services.h"

#include "dcn10_hubp.h"

#include "dcn10_hubbub.h"

#include "dcn10_hw_sequencer.h"

#include "dce110/dce110_hw_sequencer.h"

#include "dce/dce_hwseq.h"

#include "reg_helper.h"



#define CTX \

	hws->ctx

	hubbub->ctx

#define REG(reg)\

	hws->regs->reg

	hubbub->regs->reg



#undef FN

#define FN(reg_name, field_name) \

	hws->shifts->field_name, hws->masks->field_name

	hubbub->shifts->field_name, hubbub->masks->field_name



void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,

void hubbub1_wm_read_state(struct hubbub *hubbub,

		struct dcn_hubbub_wm *wm)

{

	struct dcn_hubbub_wm_set *s;
@@ -79,7 +76,7 @@ void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws, 
}



void verify_allow_pstate_change_high(

	struct dce_hwseq *hws)

	struct hubbub *hubbub)

{

	/* pstate latency is ~20us so if we wait over 40us and pstate allow

	 * still not asserted, we are probably stuck and going to hang
@@ -139,7 +136,7 @@ void verify_allow_pstate_change_high( 
		if (debug_data & (1 << 30)) {



			if (i > pstate_wait_expected_timeout_us)

				dm_logger_write(hws->ctx->logger, LOG_WARNING,

				dm_logger_write(hubbub->ctx->logger, LOG_WARNING,

						"pstate took longer than expected ~%dus\n",

						i);
@@ -160,10 +157,10 @@ void verify_allow_pstate_change_high( 
	forced_pstate_allow = true;



	if (should_log_hw_state) {

		dcn10_log_hw_state(hws->ctx->dc);

		dcn10_log_hw_state(hubbub->ctx->dc);

	}



	dm_logger_write(hws->ctx->logger, LOG_WARNING,

	dm_logger_write(hubbub->ctx->logger, LOG_WARNING,

			"pstate TEST_DEBUG_DATA: 0x%X\n",

			debug_data);

	BREAK_TO_DEBUGGER();
@@ -186,11 +183,11 @@ static uint32_t convert_and_clamp( 




void program_watermarks(

		struct dce_hwseq *hws,

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz)

{

	uint32_t force_en = hws->ctx->dc->debug.disable_stutter ? 1 : 0;

	uint32_t force_en = hubbub->ctx->dc->debug.disable_stutter ? 1 : 0;

	/*

	 * Need to clamp to max of the register values (i.e. no wrap)

	 * for dcn1, all wm registers are 21-bit wide
@@ -206,7 +203,7 @@ void program_watermarks( 
			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);



	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"URGENCY_WATERMARK_A calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->a.urgent_ns, prog_wm_value);
@@ -214,7 +211,7 @@ void program_watermarks( 
	prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"PTE_META_URGENCY_WATERMARK_A calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->a.pte_meta_urgent_ns, prog_wm_value);
@@ -224,7 +221,7 @@ void program_watermarks( 
				watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_ENTER_EXIT_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->a.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -234,7 +231,7 @@ void program_watermarks( 
				watermarks->a.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_EXIT_WATERMARK_A calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->a.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -244,7 +241,7 @@ void program_watermarks( 
			watermarks->a.cstate_pstate.pstate_change_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"DRAM_CLK_CHANGE_WATERMARK_A calculated =%d\n"

		"HW register value = 0x%x\n\n",

		watermarks->a.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -254,7 +251,7 @@ void program_watermarks( 
	prog_wm_value = convert_and_clamp(

			watermarks->b.urgent_ns, refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"URGENCY_WATERMARK_B calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->b.urgent_ns, prog_wm_value);
@@ -264,7 +261,7 @@ void program_watermarks( 
			watermarks->b.pte_meta_urgent_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"PTE_META_URGENCY_WATERMARK_B calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->b.pte_meta_urgent_ns, prog_wm_value);
@@ -275,7 +272,7 @@ void program_watermarks( 
				watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_ENTER_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->b.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -285,7 +282,7 @@ void program_watermarks( 
				watermarks->b.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_EXIT_WATERMARK_B calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->b.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -295,7 +292,7 @@ void program_watermarks( 
			watermarks->b.cstate_pstate.pstate_change_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"DRAM_CLK_CHANGE_WATERMARK_B calculated =%d\n\n"

		"HW register value = 0x%x\n",

		watermarks->b.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -304,7 +301,7 @@ void program_watermarks( 
	prog_wm_value = convert_and_clamp(

			watermarks->c.urgent_ns, refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"URGENCY_WATERMARK_C calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->c.urgent_ns, prog_wm_value);
@@ -314,7 +311,7 @@ void program_watermarks( 
			watermarks->c.pte_meta_urgent_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"PTE_META_URGENCY_WATERMARK_C calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->c.pte_meta_urgent_ns, prog_wm_value);
@@ -325,7 +322,7 @@ void program_watermarks( 
				watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_ENTER_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->c.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -335,7 +332,7 @@ void program_watermarks( 
				watermarks->c.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_EXIT_WATERMARK_C calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->c.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -345,7 +342,7 @@ void program_watermarks( 
			watermarks->c.cstate_pstate.pstate_change_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"DRAM_CLK_CHANGE_WATERMARK_C calculated =%d\n\n"

		"HW register value = 0x%x\n",

		watermarks->c.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -354,7 +351,7 @@ void program_watermarks( 
	prog_wm_value = convert_and_clamp(

			watermarks->d.urgent_ns, refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"URGENCY_WATERMARK_D calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->d.urgent_ns, prog_wm_value);
@@ -363,7 +360,7 @@ void program_watermarks( 
			watermarks->d.pte_meta_urgent_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"PTE_META_URGENCY_WATERMARK_D calculated =%d\n"

		"HW register value = 0x%x\n",

		watermarks->d.pte_meta_urgent_ns, prog_wm_value);
@@ -374,7 +371,7 @@ void program_watermarks( 
				watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_ENTER_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->d.cstate_pstate.cstate_enter_plus_exit_ns, prog_wm_value);
@@ -384,7 +381,7 @@ void program_watermarks( 
				watermarks->d.cstate_pstate.cstate_exit_ns,

				refclk_mhz, 0x1fffff);

		REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, prog_wm_value);

		dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

		dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

			"SR_EXIT_WATERMARK_D calculated =%d\n"

			"HW register value = 0x%x\n",

			watermarks->d.cstate_pstate.cstate_exit_ns, prog_wm_value);
@@ -395,7 +392,7 @@ void program_watermarks( 
			watermarks->d.cstate_pstate.pstate_change_ns,

			refclk_mhz, 0x1fffff);

	REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, prog_wm_value);

	dm_logger_write(hws->ctx->logger, LOG_BANDWIDTH_CALCS,

	dm_logger_write(hubbub->ctx->logger, LOG_BANDWIDTH_CALCS,

		"DRAM_CLK_CHANGE_WATERMARK_D calculated =%d\n"

		"HW register value = 0x%x\n\n",

		watermarks->d.cstate_pstate.pstate_change_ns, prog_wm_value);
@@ -419,8 +416,8 @@ void program_watermarks( 
#endif

}



void dcn10_update_dchub(

	struct dce_hwseq *hws,

void hubbub1_update_dchub(

	struct hubbub *hubbub,

	struct dchub_init_data *dh_data)

{

	/* TODO: port code from dal2 */
@@ -475,7 +472,7 @@ void dcn10_update_dchub( 
	dh_data->dchub_info_valid = false;

}



void toggle_watermark_change_req(struct dce_hwseq *hws)

void toggle_watermark_change_req(struct hubbub *hubbub)

{

	uint32_t watermark_change_req;
@@ -491,4 +488,23 @@ void toggle_watermark_change_req(struct dce_hwseq *hws) 
			DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, watermark_change_req);

}



static const struct hubbub_funcs hubbub1_funcs = {

	.update_dchub = hubbub1_update_dchub

};



void hubbub1_construct(struct hubbub *hubbub,

	struct dc_context *ctx,

	const struct dcn_hubbub_registers *hubbub_regs,

	const struct dcn_hubbub_shift *hubbub_shift,

	const struct dcn_hubbub_mask *hubbub_mask)

{

	hubbub->ctx = ctx;



	hubbub->funcs = &hubbub1_funcs;



	hubbub->regs = hubbub_regs;

	hubbub->shifts = hubbub_shift;

	hubbub->masks = hubbub_mask;



}

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h

+156 −6
Original line number Diff line number Diff line
@@ -28,6 +28,136 @@ 


#include "core_types.h"



#define HUBHUB_REG_LIST_DCN()\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C),\

	SR(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D),\

	SR(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D),\

	SR(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D),\

	SR(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL),\

	SR(DCHUBBUB_ARB_DRAM_STATE_CNTL),\

	SR(DCHUBBUB_ARB_SAT_LEVEL),\

	SR(DCHUBBUB_ARB_DF_REQ_OUTSTAND),\

	SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \

	SR(DCHUBBUB_TEST_DEBUG_INDEX), \

	SR(DCHUBBUB_TEST_DEBUG_DATA)



#define HUBBUB_SR_WATERMARK_REG_LIST()\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C),\

	SR(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D),\

	SR(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D)



#define HUBBUB_REG_LIST_DCN10(id)\

	HUBHUB_REG_LIST_DCN(), \

	HUBBUB_SR_WATERMARK_REG_LIST(), \

	SR(DCHUBBUB_SDPIF_FB_TOP),\

	SR(DCHUBBUB_SDPIF_FB_BASE),\

	SR(DCHUBBUB_SDPIF_FB_OFFSET),\

	SR(DCHUBBUB_SDPIF_AGP_BASE),\

	SR(DCHUBBUB_SDPIF_AGP_BOT),\

	SR(DCHUBBUB_SDPIF_AGP_TOP)



struct dcn_hubbub_registers {

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;

	uint32_t DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;

	uint32_t DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL;

	uint32_t DCHUBBUB_ARB_SAT_LEVEL;

	uint32_t DCHUBBUB_ARB_DF_REQ_OUTSTAND;

	uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL;

	uint32_t DCHUBBUB_ARB_DRAM_STATE_CNTL;

	uint32_t DCHUBBUB_TEST_DEBUG_INDEX;

	uint32_t DCHUBBUB_TEST_DEBUG_DATA;

	uint32_t DCHUBBUB_SDPIF_FB_TOP;

	uint32_t DCHUBBUB_SDPIF_FB_BASE;

	uint32_t DCHUBBUB_SDPIF_FB_OFFSET;

	uint32_t DCHUBBUB_SDPIF_AGP_BASE;

	uint32_t DCHUBBUB_SDPIF_AGP_BOT;

	uint32_t DCHUBBUB_SDPIF_AGP_TOP;

	uint32_t DCHUBBUB_CRC_CTRL;

};



/* set field name */

#define HUBBUB_SF(reg_name, field_name, post_fix)\

	.field_name = reg_name ## __ ## field_name ## post_fix





#define HUBBUB_MASK_SH_LIST_DCN(mask_sh)\

		HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL, DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_DRAM_STATE_CNTL, DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_SAT_LEVEL, DCHUBBUB_ARB_SAT_LEVEL, mask_sh), \

		HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, mask_sh)



#define HUBBUB_MASK_SH_LIST_DCN10(mask_sh)\

		HUBBUB_MASK_SH_LIST_DCN(mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_FB_TOP, SDPIF_FB_TOP, mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \

		HUBBUB_SF(DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh)



#define DCN_HUBBUB_REG_FIELD_LIST(type) \

		type DCHUBBUB_GLOBAL_TIMER_ENABLE; \

		type DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST;\

		type DCHUBBUB_ARB_WATERMARK_CHANGE_DONE_INTERRUPT_DISABLE;\

		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE;\

		type DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE;\

		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_VALUE;\

		type DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE;\

		type DCHUBBUB_ARB_SAT_LEVEL;\

		type DCHUBBUB_ARB_MIN_REQ_OUTSTAND;\

		type DCHUBBUB_GLOBAL_TIMER_REFDIV;\

		type SDPIF_FB_TOP;\

		type SDPIF_FB_BASE;\

		type SDPIF_FB_OFFSET;\

		type SDPIF_AGP_BASE;\

		type SDPIF_AGP_BOT;\

		type SDPIF_AGP_TOP





struct dcn_hubbub_shift {

	DCN_HUBBUB_REG_FIELD_LIST(uint8_t);

};



struct dcn_hubbub_mask {

	DCN_HUBBUB_REG_FIELD_LIST(uint32_t);

};



struct dc;



struct dcn_hubbub_wm_set {
@@ -43,25 +173,45 @@ struct dcn_hubbub_wm { 
	struct dcn_hubbub_wm_set sets[4];

};



void dcn10_update_dchub(

	struct dce_hwseq *hws,

struct hubbub_funcs {

	void (*update_dchub)(

			struct hubbub *hubbub,

			struct dchub_init_data *dh_data);

};



struct hubbub {

	const struct hubbub_funcs *funcs;

	struct dc_context *ctx;

	const struct dcn_hubbub_registers *regs;

	const struct dcn_hubbub_shift *shifts;

	const struct dcn_hubbub_mask *masks;

};



void hubbub1_update_dchub(

	struct hubbub *hubbub,

	struct dchub_init_data *dh_data);



void dcn10_log_hw_state(

		struct dc *dc);



void verify_allow_pstate_change_high(

	struct dce_hwseq *hws);

	struct hubbub *hubbub);



void program_watermarks(

		struct dce_hwseq *hws,

		struct hubbub *hubbub,

		struct dcn_watermark_set *watermarks,

		unsigned int refclk_mhz);



void toggle_watermark_change_req(

		struct dce_hwseq *hws);

		struct hubbub *hubbub);



void dcn10_hubbub_wm_read_state(struct dce_hwseq *hws,

void hubbub1_wm_read_state(struct hubbub *hubbub,

		struct dcn_hubbub_wm *wm);



void hubbub1_construct(struct hubbub *hubbub,

	struct dc_context *ctx,

	const struct dcn_hubbub_registers *hubbub_regs,

	const struct dcn_hubbub_shift *hubbub_shift,

	const struct dcn_hubbub_mask *hubbub_mask);



#endif

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+22 −23
Original line number Diff line number Diff line
@@ -87,7 +87,7 @@ void dcn10_log_hubbub_state(struct dc *dc) 
	struct dcn_hubbub_wm wm;

	int i;



	dcn10_hubbub_wm_read_state(dc->hwseq, &wm);

	hubbub1_wm_read_state(dc->res_pool->hubbub, &wm);



	DTN_INFO("HUBBUB WM: \t data_urgent \t pte_meta_urgent \t "

			"sr_enter \t sr_exit \t dram_clk_change \n");
@@ -571,10 +571,10 @@ static void plane_atomic_disconnect(struct dc *dc, 
		return;



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	hubp->funcs->dcc_control(hubp, false, false);

	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);



	mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree),

			dc->res_pool->opps[opp_id]->inst, fe_idx);
@@ -602,7 +602,7 @@ static void plane_atomic_disable(struct dc *dc, 
	hubp->funcs->set_blank(hubp, true);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);



	REG_UPDATE(HUBP_CLK_CNTL[fe_idx],

			HUBP_CLOCK_ENABLE, 0);
@@ -614,7 +614,7 @@ static void plane_atomic_disable(struct dc *dc, 
				OPP_PIPE_CLOCK_EN, 0);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

}



static void reset_front_end(
@@ -638,7 +638,7 @@ static void reset_front_end( 
	tg->funcs->unlock(tg);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(hws);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);



	if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)

		REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst],
@@ -670,7 +670,7 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) 
			"Power gated front end %d\n", fe_idx);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

}



static void dcn10_init_hw(struct dc *dc)
@@ -1243,7 +1243,7 @@ static void dcn10_pipe_control_lock( 
		return;



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);



	if (lock)

		pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
@@ -1251,7 +1251,7 @@ static void dcn10_pipe_control_lock( 
		pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

}



static bool wait_for_reset_trigger_to_occur(
@@ -1451,7 +1451,7 @@ static void dcn10_power_on_fe( 
	struct dce_hwseq *hws = dc->hwseq;



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



	power_on_plane(dc->hwseq,
@@ -1503,7 +1503,7 @@ static void dcn10_power_on_fe( 
	}



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}

}
@@ -1864,11 +1864,11 @@ static void program_all_pipe_in_tree( 
		 * this OTG. this is done only one time.

		 */

		/* watermark is for all pipes */

		program_watermarks(dc->hwseq, &context->bw.dcn.watermarks, ref_clk_mhz);

		program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz);



		if (dc->debug.sanity_checks) {

			/* pstate stuck check after watermark update */

			verify_allow_pstate_change_high(dc->hwseq);

			verify_allow_pstate_change_high(dc->res_pool->hubbub);

		}



		pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
@@ -1899,7 +1899,7 @@ static void program_all_pipe_in_tree( 
		 * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have

		 * both driver and fw accessing same register

		 */

		toggle_watermark_change_req(dc->hwseq);

		toggle_watermark_change_req(dc->res_pool->hubbub);



		update_dchubp_dpp(dc, pipe_ctx, context);
@@ -1922,7 +1922,7 @@ static void program_all_pipe_in_tree( 


	if (dc->debug.sanity_checks) {

		/* pstate stuck check after each pipe is programmed */

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



	if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
@@ -1989,7 +1989,7 @@ static void dcn10_apply_ctx_for_surface( 
	int i, be_idx;



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);



	be_idx = -1;

	for (i = 0; i < dc->res_pool->pipe_count; i++) {
@@ -2072,7 +2072,7 @@ static void dcn10_apply_ctx_for_surface( 
				hubp->funcs->hubp_disconnect(hubp);



			if (dc->debug.sanity_checks)

				verify_allow_pstate_change_high(dc->hwseq);

				verify_allow_pstate_change_high(dc->res_pool->hubbub);



			old_pipe_ctx->top_pipe = NULL;

			old_pipe_ctx->bottom_pipe = NULL;
@@ -2150,7 +2150,7 @@ static void dcn10_apply_ctx_for_surface( 
			);



	if (dc->debug.sanity_checks)

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

}



static void dcn10_set_bandwidth(
@@ -2164,7 +2164,7 @@ static void dcn10_set_bandwidth( 
	struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
@@ -2220,7 +2220,7 @@ static void dcn10_set_bandwidth( 
	dcn10_pplib_apply_display_requirements(dc, context);



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



	/* need to fix this function.  not doing the right thing here */
@@ -2345,7 +2345,7 @@ static void dcn10_wait_for_mpcc_disconnect( 
	int i;



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



	if (!pipe_ctx->stream_res.opp)
@@ -2363,7 +2363,7 @@ static void dcn10_wait_for_mpcc_disconnect( 
	}



	if (dc->debug.sanity_checks) {

		verify_allow_pstate_change_high(dc->hwseq);

		verify_allow_pstate_change_high(dc->res_pool->hubbub);

	}



}
@@ -2407,7 +2407,6 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,

	.set_plane_config = set_plane_config,

	.update_plane_addr = dcn10_update_plane_addr,

	.update_dchub = dcn10_update_dchub,

	.update_pending_status = dcn10_update_pending_status,

	.set_input_transfer_func = dcn10_set_input_transfer_func,

	.set_output_transfer_func = dcn10_set_output_transfer_func,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

+38 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 
#include "dce110/dce110_resource.h"

#include "dce112/dce112_resource.h"

#include "dcn10_hubp.h"

#include "dcn10_hubbub.h"



#include "vega10/soc15ip.h"
@@ -388,6 +389,19 @@ static const struct dcn_mi_mask hubp_mask = { 
		HUBP_MASK_SH_LIST_DCN10(_MASK)

};





static const struct dcn_hubbub_registers hubbub_reg = {

		HUBBUB_REG_LIST_DCN10(0)

};



static const struct dcn_hubbub_shift hubbub_shift = {

		HUBBUB_MASK_SH_LIST_DCN10(__SHIFT)

};



static const struct dcn_hubbub_mask hubbub_mask = {

		HUBBUB_MASK_SH_LIST_DCN10(_MASK)

};



#define clk_src_regs(index, pllid)\

[index] = {\

	CS_COMMON_REG_LIST_DCN1_0(index, pllid),\
@@ -519,6 +533,22 @@ static struct mpc *dcn10_mpc_create(struct dc_context *ctx) 
	return &mpc10->base;

}



static struct hubbub *dcn10_hubbub_create(struct dc_context *ctx)

{

	struct hubbub *hubbub = kzalloc(sizeof(struct hubbub),

					  GFP_KERNEL);



	if (!hubbub)

		return NULL;



	hubbub1_construct(hubbub, ctx,

			&hubbub_reg,

			&hubbub_shift,

			&hubbub_mask);



	return hubbub;

}



static struct timing_generator *dcn10_timing_generator_create(

		struct dc_context *ctx,

		uint32_t instance)
@@ -1401,6 +1431,7 @@ static bool construct( 
			dm_error("DC: failed to create tg!\n");

			goto fail;

		}



		/* check next valid pipe */

		j++;

	}
@@ -1421,6 +1452,13 @@ static bool construct( 
		goto fail;

	}



	pool->base.hubbub = dcn10_hubbub_create(ctx);

	if (pool->base.mpc == NULL) {

		BREAK_TO_DEBUGGER();

		dm_error("DC: failed to create mpc!\n");

		goto fail;

	}



	if (!resource_construct(num_virtual_links, dc, &pool->base,

			(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?

			&res_create_funcs : &res_create_maximus_funcs)))

drivers/gpu/drm/amd/display/dc/inc/core_types.h

+1 −0
Original line number Diff line number Diff line
@@ -139,6 +139,7 @@ struct resource_pool { 
	struct timing_generator *timing_generators[MAX_PIPES];

	struct stream_encoder *stream_enc[MAX_PIPES * 2];



	struct hubbub *hubbub;

	struct mpc *mpc;

	struct pp_smu_funcs_rv *pp_smu;

	struct pp_smu_display_requirement_rv pp_smu_req;