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Commit c9214f50 authored by David S. Miller's avatar David S. Miller
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Merge branch 'mvneta-hwbm'

Gregory CLEMENT says:

====================
API set for HW Buffer management

This is the sixth version of the API set for HW Buffer management (that was
initially submitted here:
http://thread.gmane.org/gmane.linux.kernel/2125152

).

This version is just a rebasing onto the last net-next. I also added
the Tested-by flag from Sebastian Careba : "The patch set applies
successfully and it works well, no more Samba issues any longer".

For the record in the previous versions I made the following changes:
v4 -> v5:
- Add a field with the size of the buffer of the pool was added. It
  then allow to fix some misused size in the mvneta_bm code when using
  the new framework.

- Add a new patch from Marcin for sram allowing to require
  non-bufferable access to the memory. It was needed for the hardware
  buffer management of the mvneta.

- Fix the build issue notified by the 0-day builder when building the
  drivers as module.

v3 -> v4
- Fix build issue when HWBM is not selected

v2 -> v3
- Make a HWBM and a SWBM version of the mvneta_rx() function in order
  to reduce the the conditional code. Kept a condition inside the
  mvneta_poll because specializing this function would have means
  duplicating 95% of the code.

- Put back the register_netdev() call at the end of the mvneta_probe()
  function. In order to have a unique ID for each port, just used a
  global variable in the driver.

- Added a fix from Marcin in the "net: mvneta: bm: add support for
  hardware buffer management" patch: "when dropping packets, only
  buffer pointers passed from BM to descriptors have to be returned to
  the pool. In submitted version after closing the port and
  mvneta_rxq_deinit(), it was very likely that a lot of fake buffers
  are added to the pool, because all descriptors took part in
  iteration."

- Removed the select MVNETA_BM from the Kconfig, it will let the user
  the choice to use not use it if they want.

v1 -> v2
- The hardware buffer management helpers are no more built by default
  and now depend on a hidden config symbol which has to be selected
  by the driver if needed
- The hwbm_pool_refill() and hwbm_pool_add() now receive a gfp_t as
  argument allowing the caller to specify the flag it needs.
- buf_num is now tested to ensure there is no wrapping
- A spinlock has been added to protect the hwbm_pool_add() function in
  SMP or irq context.
- used pr_warn instead of pr_debug in case of errors.
- fixed the mvneta implementation by returning the buffer to the pool
  at various place instead of ignoring it.
- Squashed "bus: mvenus-mbus: Fix size test for
   mvebu_mbus_get_dram_win_info" into bus: mvebu-mbus: provide api for
   obtaining IO and DRAM window information.
- Added my signed-otf-by on all the patches as submitter of the series.
- Renamed the dts patches with the pattern "ARM: dts: platform:"
- Removed the patch "ARM: mvebu: enable SRAM support in
  mvebu_v7_defconfig" of this series and already applied it
- Modified the order of the patches.

In order to ease the test the branch mvneta-BM-framework-v6 is
available at git@github.com:MISL-EBU-System-SW/mainline-public.git.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents d3bf9b19 baa11ebc
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+17 −2
Original line number Diff line number Diff line
@@ -18,15 +18,30 @@ Optional properties:
  "core" for core clock and "bus" for the optional bus clock.


Optional properties (valid only for Armada XP/38x):

- buffer-manager: a phandle to a buffer manager node. Please refer to
  Documentation/devicetree/bindings/net/marvell-neta-bm.txt
- bm,pool-long: ID of a pool, that will accept all packets of a size
  higher than 'short' pool's threshold (if set) and up to MTU value.
  Obligatory, when the port is supposed to use hardware
  buffer management.
- bm,pool-short: ID of a pool, that will be used for accepting
  packets of a size lower than given threshold. If not set, the port
  will use a single 'long' pool for all packets, as defined above.

Example:

ethernet@d0070000 {
ethernet@70000 {
	compatible = "marvell,armada-370-neta";
	reg = <0xd0070000 0x2500>;
	reg = <0x70000 0x2500>;
	interrupts = <8>;
	clocks = <&gate_clk 4>;
	tx-csum-limit = <9800>
	status = "okay";
	phy = <&phy0>;
	phy-mode = "rgmii-id";
	buffer-manager = <&bm>;
	bm,pool-long = <0>;
	bm,pool-short = <1>;
};
+49 −0
Original line number Diff line number Diff line
* Marvell Armada 380/XP Buffer Manager driver (BM)

Required properties:

- compatible: should be "marvell,armada-380-neta-bm".
- reg: address and length of the register set for the device.
- clocks: a pointer to the reference clock for this device.
- internal-mem: a phandle to BM internal SRAM definition.

Optional properties (port):

- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
  in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
  to be chosen between 128 and 16352 and it also has to be aligned to 32.
  Otherwise the driver would adjust a given number or choose default if
  not set.
- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
  pointers' pool (id 0 : 3). It will be taken into consideration only when pool
  type is 'short'. For 'long' ones it would be overridden by port's MTU.
  If not set a driver will choose a default value.

In order to see how to hook the BM to a given ethernet port, please
refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.

Example:

- main node:

bm: bm@c8000 {
	compatible = "marvell,armada-380-neta-bm";
	reg = <0xc8000 0xac>;
	clocks = <&gateclk 13>;
	internal-mem = <&bm_bppi>;
	status = "okay";
	pool2,capacity = <4096>;
	pool1,pkt-size = <512>;
};

- internal SRAM node:

bm_bppi: bm-bppi {
	compatible = "mmio-sram";
	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
	#address-cells = <1>;
	#size-cells = <1>;
	clocks = <&gateclk 13>;
	status = "okay";
};
+5 −0
Original line number Diff line number Diff line
@@ -25,6 +25,11 @@ Required properties in the sram node:
- ranges : standard definition, should translate from local addresses
           within the sram to bus addresses

Optional properties in the sram node:

- no-memory-wc : the flag indicating, that SRAM memory region has not to
                 be remapped as write combining. WC is used by default.

Required properties in the area nodes:

- reg : iomem address range, relative to the SRAM range
+19 −1
Original line number Diff line number Diff line
@@ -61,7 +61,8 @@
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			spi1: spi@10680 {
@@ -138,12 +139,18 @@
				status = "okay";
				phy = <&phy2>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <1>;
				bm,pool-short = <3>;
			};

			ethernet@34000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <3>;
			};

			ethernet@70000 {
@@ -157,6 +164,13 @@
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
				bm,pool-short = <3>;
			};

			bm@c8000 {
				status = "okay";
			};

			nfc: flash@d0000 {
@@ -178,6 +192,10 @@
			};
		};

		bm-bppi {
			status = "okay";
		};

		pcie-controller {
			status = "okay";

+6 −0
Original line number Diff line number Diff line
@@ -78,6 +78,9 @@
		internal-regs {
			ethernet@30000 {
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <1>;
				status = "okay";

				fixed-link {
@@ -88,6 +91,9 @@

			ethernet@34000 {
				phy-mode = "sgmii";
				buffer-manager = <&bm>;
				bm,pool-long = <3>;
				bm,pool-short = <1>;
				status = "okay";

				fixed-link {
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