Commit c901e45a authored Nov 28, 2017 by Palmer Dabbelt

RISC-V: `sfence.vma` orderes the instruction cache



This is just a comment change, but it's one that bit me on the mailing
list.  It turns out that issuing a `sfence.vma` enforces instruction
cache ordering in addition to TLB ordering.  This isn't explicitly
called out in the ISA manual, but Andrew will be making that more clear
in a future revision.

CC: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 21db4036

arch/riscv/include/asm/tlbflush.h

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -17,7 +17,10 @@

	#ifdef CONFIG_MMU		#ifdef CONFIG_MMU

	/* Flush entire local TLB */		/*
			* Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
			* cache as well, so a 'fence.i' is not necessary.
			*/
	static inline void local_flush_tlb_all(void)		static inline void local_flush_tlb_all(void)
	{		{
	__asm__ __volatile__ ("sfence.vma" : : : "memory");		__asm__ __volatile__ ("sfence.vma" : : : "memory");