Loading qcom/msm-arm-smmu-lagoon.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,10 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, Loading Loading @@ -192,4 +196,23 @@ qcom,stream-id-range = <0x1800 0x400>; }; }; kgsl_iommu_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&kgsl_smmu 0x7>; }; apps_iommu_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&apps_smmu 0x1 0>; }; apps_iommu_coherent_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&apps_smmu 0x3 0>; dma-coherent; }; }; Loading
qcom/msm-arm-smmu-lagoon.dtsi +23 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,10 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, Loading Loading @@ -192,4 +196,23 @@ qcom,stream-id-range = <0x1800 0x400>; }; }; kgsl_iommu_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&kgsl_smmu 0x7>; }; apps_iommu_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&apps_smmu 0x1 0>; }; apps_iommu_coherent_test_device { compatible = "iommu-debug-test"; qcom,iommu-dma = "disabled"; iommus = <&apps_smmu 0x3 0>; dma-coherent; }; };