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Commit c8d9a590 authored by Deepak S's avatar Deepak S Committed by Daniel Vetter
Browse files

drm/i915: Add power well arguments to force wake routines. 



Added power well arguments to all the force wake routines
to help us individually control power well based on the
scenario.

Signed-off-by: default avatarDeepak S <deepak.s@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Resolve conflict with the removed forcewake hack and drop one
spurious hunk Jesse noticed.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 947fdaad

drivers/gpu/drm/i915/i915_debugfs.c

+4 −4
Original line number Diff line number Diff line
@@ -947,7 +947,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
		if (ret)

			return ret;



		gen6_gt_force_wake_get(dev_priv);

		gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



		reqf = I915_READ(GEN6_RPNSWREQ);

		reqf &= ~GEN6_TURBO_DISABLE;
@@ -970,7 +970,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
			cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;

		cagf *= GT_FREQUENCY_MULTIPLIER;



		gen6_gt_force_wake_put(dev_priv);

		gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

		mutex_unlock(&dev->struct_mutex);



		seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
@@ -3053,7 +3053,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) 
	if (INTEL_INFO(dev)->gen < 6)

		return 0;



	gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	return 0;

}
@@ -3066,7 +3066,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) 
	if (INTEL_INFO(dev)->gen < 6)

		return 0;



	gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);



	return 0;

}

drivers/gpu/drm/i915/i915_drv.h

+11 −4
Original line number Diff line number Diff line
@@ -437,8 +437,10 @@ struct drm_i915_display_funcs { 
};



struct intel_uncore_funcs {

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

	void (*force_wake_get)(struct drm_i915_private *dev_priv,

							int fw_engine);

	void (*force_wake_put)(struct drm_i915_private *dev_priv,

							int fw_engine);



	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);

	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
@@ -2438,8 +2440,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 
 * must be set to prevent GT core from power down and stale values being

 * returned.

 */

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);



int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);

int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
@@ -2468,6 +2470,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 
int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);

int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);



#define FORCEWAKE_RENDER	(1 << 0)

#define FORCEWAKE_MEDIA		(1 << 1)

#define FORCEWAKE_ALL		(FORCEWAKE_RENDER | FORCEWAKE_MEDIA)





#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)

#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

drivers/gpu/drm/i915/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -6583,7 +6583,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 


	/* Make sure we're not on PC8 state before disabling PC8, otherwise

	 * we'll hang the machine! */

	dev_priv->uncore.funcs.force_wake_get(dev_priv);

	dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);



	if (val & LCPLL_POWER_DOWN_ALLOW) {

		val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -6617,7 +6617,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 
			DRM_ERROR("Switching back to LCPLL failed\n");

	}



	dev_priv->uncore.funcs.force_wake_put(dev_priv);

	dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);

}



void hsw_enable_pc8_work(struct work_struct *__work)

drivers/gpu/drm/i915/intel_pm.c

+11 −8
Original line number Diff line number Diff line
@@ -191,7 +191,8 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) 
	u32 blt_ecoskpd;



	/* Make sure blitter notifies FBC of writes */

	gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);

	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<

		GEN6_BLITTER_LOCK_SHIFT;
@@ -202,7 +203,8 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev) 
			 GEN6_BLITTER_LOCK_SHIFT);

	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

	POSTING_READ(GEN6_BLITTER_ECOSKPD);

	gen6_gt_force_wake_put(dev_priv);



	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

}



static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -3739,7 +3741,7 @@ static void gen8_enable_rps(struct drm_device *dev) 


	/* 1c & 1d: Get forcewake during program sequence. Although the driver

	 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/

	gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	/* 2a: Disable RC states. */

	I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -3796,7 +3798,7 @@ static void gen8_enable_rps(struct drm_device *dev) 


	gen6_enable_rps_interrupts(dev);



	gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

}



static void gen6_enable_rps(struct drm_device *dev)
@@ -3826,7 +3828,7 @@ static void gen6_enable_rps(struct drm_device *dev) 
		I915_WRITE(GTFIFODBG, gtfifodbg);

	}



	gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);

	gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
@@ -3918,7 +3920,7 @@ static void gen6_enable_rps(struct drm_device *dev) 
			DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");

	}



	gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

}



void gen6_update_ring_freq(struct drm_device *dev)
@@ -4080,7 +4082,8 @@ static void valleyview_enable_rps(struct drm_device *dev) 


	valleyview_setup_pctx(dev);



	gen6_gt_force_wake_get(dev_priv);

	/* If VLV, Forcewake all wells, else re-direct to regular path */

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);

	I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -4152,7 +4155,7 @@ static void valleyview_enable_rps(struct drm_device *dev) 


	gen6_enable_rps_interrupts(dev);



	gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);

}



void ironlake_teardown_rc6(struct drm_device *dev)

drivers/gpu/drm/i915/intel_ringbuffer.c

+2 −2
Original line number Diff line number Diff line
@@ -438,7 +438,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) 
	int ret = 0;

	u32 head;



	gen6_gt_force_wake_get(dev_priv);

	gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);



	if (I915_NEED_GFX_HWS(dev))

		intel_ring_setup_status_page(ring);
@@ -511,7 +511,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) 
	memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));



out:

	gen6_gt_force_wake_put(dev_priv);

	gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);



	return ret;

}