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Commit c8d48d9c authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
Browse files

r8169: improve pci region handling 



The region to be used is always the first of type IORESOURCE_MEM.
We can implement this rule directly w/o having to specify which
region is the first one per configuration entry.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a4328ddb

drivers/net/ethernet/realtek/r8169.c

+5 −11
Original line number Original line Diff line number Diff line
@@ -7974,7 +7974,6 @@ static const struct net_device_ops rtl_netdev_ops = { 




static const struct rtl_cfg_info {

static const struct rtl_cfg_info {

	void (*hw_start)(struct rtl8169_private *tp);

	void (*hw_start)(struct rtl8169_private *tp);

	unsigned int region;

	u16 event_slow;

	u16 event_slow;

	unsigned int has_gmii:1;

	unsigned int has_gmii:1;

	const struct rtl_coalesce_info *coalesce_info;

	const struct rtl_coalesce_info *coalesce_info;
@@ -7982,7 +7981,6 @@ static const struct rtl_cfg_info { 
} rtl_cfg_infos [] = {

} rtl_cfg_infos [] = {

	[RTL_CFG_0] = {

	[RTL_CFG_0] = {

		.hw_start	= rtl_hw_start_8169,

		.hw_start	= rtl_hw_start_8169,

		.region		= 1,

		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,

		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver,

		.has_gmii	= 1,

		.has_gmii	= 1,

		.coalesce_info	= rtl_coalesce_info_8169,

		.coalesce_info	= rtl_coalesce_info_8169,
@@ -7990,7 +7988,6 @@ static const struct rtl_cfg_info { 
	},

	},

	[RTL_CFG_1] = {

	[RTL_CFG_1] = {

		.hw_start	= rtl_hw_start_8168,

		.hw_start	= rtl_hw_start_8168,

		.region		= 2,

		.event_slow	= SYSErr | LinkChg | RxOverflow,

		.event_slow	= SYSErr | LinkChg | RxOverflow,

		.has_gmii	= 1,

		.has_gmii	= 1,

		.coalesce_info	= rtl_coalesce_info_8168_8136,

		.coalesce_info	= rtl_coalesce_info_8168_8136,
@@ -7998,7 +7995,6 @@ static const struct rtl_cfg_info { 
	},

	},

	[RTL_CFG_2] = {

	[RTL_CFG_2] = {

		.hw_start	= rtl_hw_start_8101,

		.hw_start	= rtl_hw_start_8101,

		.region		= 2,

		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |

		.event_slow	= SYSErr | LinkChg | RxOverflow | RxFIFOOver |

				  PCSTimeout,

				  PCSTimeout,

		.coalesce_info	= rtl_coalesce_info_8168_8136,

		.coalesce_info	= rtl_coalesce_info_8168_8136,
@@ -8098,11 +8094,10 @@ static void rtl_hw_initialize(struct rtl8169_private *tp) 
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)

static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)

{

{

	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;

	const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;

	const unsigned int region = cfg->region;

	struct rtl8169_private *tp;

	struct rtl8169_private *tp;

	struct mii_if_info *mii;

	struct mii_if_info *mii;

	struct net_device *dev;

	struct net_device *dev;

	int chipset, i;

	int chipset, region, i;

	int rc;

	int rc;





	if (netif_msg_drv(&debug)) {

	if (netif_msg_drv(&debug)) {
@@ -8144,11 +8139,10 @@ static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	if (pcim_set_mwi(pdev) < 0)

	if (pcim_set_mwi(pdev) < 0)

		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");

		netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");





	/* make sure PCI base addr 1 is MMIO */

	/* use first MMIO region */

	if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {

	region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;

		netif_err(tp, probe, dev,

	if (region < 0) {

			  "region #%d not an MMIO resource, aborting\n",

		netif_err(tp, probe, dev, "no MMIO resource found\n");

			  region);

		return -ENODEV;

		return -ENODEV;

	}

	}