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Commit c88b8062 authored by Vivek Aknurwar's avatar Vivek Aknurwar Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add cdiv clocks for gcc, video and camera cc driver for KONA 



Add cdiv support for gcc, video cc, camera cc and general updates
for clk frequency plan and aligning DFS clock macro to support
rcg dfs struct in one struct to initialize init element
by using hw clk init. Rename GCC_VIDEO_AXI0_CLK_BCR,
GCC_VIDEO_AXI1_CLK_BCR to respective _CLK_ARES as they doesn’t exists.

Change-Id: Ic2c4b7448d4eb8d0d1876dcbdb909e718bbca25a
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 0bfc858f

drivers/clk/qcom/camcc-kona.c

+18 −3
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.*/

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.*/



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -22,6 +22,7 @@ 
#include "clk-pll.h"

#include "clk-rcg.h"

#include "clk-regmap.h"

#include "clk-regmap-divider.h"

#include "common.h"

#include "reset.h"

#include "vdd-level.h"
@@ -437,6 +438,18 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { 
	},

};



static struct clk_regmap_div cam_cc_sbi_div_clk_src = {

	.reg = 0x9010,

	.shift = 0,

	.width = 3,

	.clkr.hw.init = &(struct clk_init_data) {

		.name = "cam_cc_sbi_div_clk_src",

		.parent_names = (const char *[]){ "cam_cc_ife_0_clk_src" },

		.num_parents = 1,

		.ops = &clk_regmap_div_ro_ops,

	},

};



static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {

	F(19200000, P_BI_TCXO, 1, 0, 0),

	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
@@ -1179,6 +1192,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = { 
	.hid_width = 5,

	.parent_map = cam_cc_parent_map_0,

	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,

	.enable_safe_config = true,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "cam_cc_slow_ahb_clk_src",

		.parent_names = cam_cc_parent_names_0,
@@ -1358,7 +1372,7 @@ static struct clk_branch cam_cc_cci_1_clk = { 


static struct clk_branch cam_cc_core_ahb_clk = {

	.halt_reg = 0xc150,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0xc150,

		.enable_mask = BIT(0),
@@ -2301,7 +2315,7 @@ static struct clk_branch cam_cc_sbi_clk = { 
		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_sbi_clk",

			.parent_names = (const char *[]){

				"cam_cc_ife_0_clk_src",

				"cam_cc_sbi_div_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,
@@ -2505,6 +2519,7 @@ static struct clk_regmap *cam_cc_kona_clocks[] = { 
	[CAM_CC_SBI_CPHY_RX_CLK] = &cam_cc_sbi_cphy_rx_clk.clkr,

	[CAM_CC_SBI_CSID_CLK] = &cam_cc_sbi_csid_clk.clkr,

	[CAM_CC_SBI_CSID_CLK_SRC] = &cam_cc_sbi_csid_clk_src.clkr,

	[CAM_CC_SBI_DIV_CLK_SRC] = &cam_cc_sbi_div_clk_src.clkr,

	[CAM_CC_SBI_IFE_0_CLK] = &cam_cc_sbi_ife_0_clk.clkr,

	[CAM_CC_SBI_IFE_1_CLK] = &cam_cc_sbi_ife_1_clk.clkr,

	[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,

drivers/clk/qcom/clk-rcg.h

+3 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved. */

/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2013, 2018-2019, The Linux Foundation. All rights reserved. */



#ifndef __QCOM_CLK_RCG_H__

#define __QCOM_CLK_RCG_H__
@@ -179,7 +179,7 @@ struct clk_rcg_dfs_data { 
};



#define DEFINE_RCG_DFS(r) \

	{ .rcg = &r##_src, .init = &r##_init }

	{ .rcg = &r, .init = &r##_init }



extern int qcom_cc_register_rcg_dfs(struct regmap *regmap,

				    const struct clk_rcg_dfs_data *rcgs,