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Commit c7dd15b3 authored by Jim Mattson's avatar Jim Mattson Committed by Radim Krčmář
Browse files

kvm: x86: CPUID.01H:EDX.APIC[bit 9] should mirror IA32_APIC_BASE[11] 



From the Intel SDM, volume 3, section 10.4.3, "Enabling or Disabling the
Local APIC,"

  When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent
  to an IA-32 processor without an on-chip APIC. The CPUID feature flag
  for the APIC (see Section 10.4.2, "Presence of the Local APIC") is
  also set to 0.

Signed-off-by: default avatarJim Mattson <jmattson@google.com>
[Changed subject tag from nVMX to x86.]
Signed-off-by: default avatarRadim Krčmář <rkrcmar@redhat.com>
parent 4504b5c9

arch/x86/kvm/cpuid.c

+4 −0
Original line number Diff line number Diff line
@@ -87,6 +87,10 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu) 
			best->ecx |= F(OSXSAVE);

	}



	best->edx &= ~F(APIC);

	if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)

		best->edx |= F(APIC);



	if (apic) {

		if (best->ecx & F(TSC_DEADLINE_TIMER))

			apic->lapic_timer.timer_mode_mask = 3 << 17;

arch/x86/kvm/lapic.c

+7 −4
Original line number Diff line number Diff line
@@ -1806,14 +1806,17 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) 
	u64 old_value = vcpu->arch.apic_base;

	struct kvm_lapic *apic = vcpu->arch.apic;



	if (!apic) {

	if (!apic)

		value |= MSR_IA32_APICBASE_BSP;

		vcpu->arch.apic_base = value;

		return;

	}



	vcpu->arch.apic_base = value;



	if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)

		kvm_update_cpuid(vcpu);



	if (!apic)

		return;



	/* update jump label if enable bit changes */

	if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {

		if (value & MSR_IA32_APICBASE_ENABLE) {