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Commit c7113cc3 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

drm/i915: unify ring irq refcounts (again) 



With the simplified locking there's no reason any more to keep the
refcounts seperate.

v2: Readd the lost comment that ring->irq_refcount is protected by
dev_priv->irq_lock.

Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 59cdb63d

drivers/gpu/drm/i915/intel_ringbuffer.c

+10 −10
Original line number Diff line number Diff line
@@ -821,7 +821,7 @@ gen5_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount.gt++ == 0) {

	if (ring->irq_refcount++ == 0) {

		dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

		POSTING_READ(GTIMR);
@@ -839,7 +839,7 @@ gen5_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount.gt == 0) {

	if (--ring->irq_refcount == 0) {

		dev_priv->gt_irq_mask |= ring->irq_enable_mask;

		I915_WRITE(GTIMR, dev_priv->gt_irq_mask);

		POSTING_READ(GTIMR);
@@ -858,7 +858,7 @@ i9xx_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount.gt++ == 0) {

	if (ring->irq_refcount++ == 0) {

		dev_priv->irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE(IMR, dev_priv->irq_mask);

		POSTING_READ(IMR);
@@ -876,7 +876,7 @@ i9xx_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount.gt == 0) {

	if (--ring->irq_refcount == 0) {

		dev_priv->irq_mask |= ring->irq_enable_mask;

		I915_WRITE(IMR, dev_priv->irq_mask);

		POSTING_READ(IMR);
@@ -895,7 +895,7 @@ i8xx_ring_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount.gt++ == 0) {

	if (ring->irq_refcount++ == 0) {

		dev_priv->irq_mask &= ~ring->irq_enable_mask;

		I915_WRITE16(IMR, dev_priv->irq_mask);

		POSTING_READ16(IMR);
@@ -913,7 +913,7 @@ i8xx_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount.gt == 0) {

	if (--ring->irq_refcount == 0) {

		dev_priv->irq_mask |= ring->irq_enable_mask;

		I915_WRITE16(IMR, dev_priv->irq_mask);

		POSTING_READ16(IMR);
@@ -1006,7 +1006,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) 
	gen6_gt_force_wake_get(dev_priv);



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount.gt++ == 0) {

	if (ring->irq_refcount++ == 0) {

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring,

				       ~(ring->irq_enable_mask |
@@ -1030,7 +1030,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) 
	unsigned long flags;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount.gt == 0) {

	if (--ring->irq_refcount == 0) {

		if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)

			I915_WRITE_IMR(ring,

				       ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
@@ -1056,7 +1056,7 @@ hsw_vebox_get_irq(struct intel_ring_buffer *ring) 
		return false;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (ring->irq_refcount.pm++ == 0) {

	if (ring->irq_refcount++ == 0) {

		u32 pm_imr = I915_READ(GEN6_PMIMR);

		I915_WRITE_IMR(ring, ~ring->irq_enable_mask);

		I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
@@ -1078,7 +1078,7 @@ hsw_vebox_put_irq(struct intel_ring_buffer *ring) 
		return;



	spin_lock_irqsave(&dev_priv->irq_lock, flags);

	if (--ring->irq_refcount.pm == 0) {

	if (--ring->irq_refcount == 0) {

		u32 pm_imr = I915_READ(GEN6_PMIMR);

		I915_WRITE_IMR(ring, ~0);

		I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);

drivers/gpu/drm/i915/intel_ringbuffer.h

+1 −4
Original line number Diff line number Diff line
@@ -78,10 +78,7 @@ struct intel_ring_buffer { 
	 */

	u32		last_retired_head;



	struct {

		u32	gt; /*  protected by dev_priv->irq_lock */

		u32	pm; /*  protected by dev_priv->irq_lock */

	} irq_refcount;

	unsigned irq_refcount; /* protected by dev_priv->irq_lock */

	u32		irq_enable_mask;	/* bitmask to enable ring interrupt */

	u32		trace_irq_seqno;

	u32		sync_seqno[I915_NUM_RINGS-1];