Loading arch/arm/include/asm/cp15.h +0 −4 Original line number Diff line number Diff line Loading @@ -80,10 +80,6 @@ static inline void set_auxcr(unsigned int val) isb(); } #ifndef CONFIG_SMP extern void adjust_cr(unsigned long mask, unsigned long set); #endif #define CPACC_FULL(n) (3 << (n * 2)) #define CPACC_SVC(n) (1 << (n * 2)) #define CPACC_DISABLE(n) (0 << (n * 2)) Loading arch/arm/mm/mmu.c +0 −20 Original line number Diff line number Diff line Loading @@ -186,26 +186,6 @@ static int __init early_ecc(char *p) early_param("ecc", early_ecc); #endif #ifndef CONFIG_SMP void adjust_cr(unsigned long mask, unsigned long set) { unsigned long flags; mask &= ~CR_A; set &= mask; local_irq_save(flags); cr_no_alignment = (cr_no_alignment & ~mask) | set; cr_alignment = (cr_alignment & ~mask) | set; set_cr((get_cr() & ~mask) | set); local_irq_restore(flags); } #endif #else /* ifdef CONFIG_CPU_CP15 */ static int __init early_cachepolicy(char *p) Loading Loading
arch/arm/include/asm/cp15.h +0 −4 Original line number Diff line number Diff line Loading @@ -80,10 +80,6 @@ static inline void set_auxcr(unsigned int val) isb(); } #ifndef CONFIG_SMP extern void adjust_cr(unsigned long mask, unsigned long set); #endif #define CPACC_FULL(n) (3 << (n * 2)) #define CPACC_SVC(n) (1 << (n * 2)) #define CPACC_DISABLE(n) (0 << (n * 2)) Loading
arch/arm/mm/mmu.c +0 −20 Original line number Diff line number Diff line Loading @@ -186,26 +186,6 @@ static int __init early_ecc(char *p) early_param("ecc", early_ecc); #endif #ifndef CONFIG_SMP void adjust_cr(unsigned long mask, unsigned long set) { unsigned long flags; mask &= ~CR_A; set &= mask; local_irq_save(flags); cr_no_alignment = (cr_no_alignment & ~mask) | set; cr_alignment = (cr_alignment & ~mask) | set; set_cr((get_cr() & ~mask) | set); local_irq_restore(flags); } #endif #else /* ifdef CONFIG_CPU_CP15 */ static int __init early_cachepolicy(char *p) Loading