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Commit c6c14277 authored by Urvashi Agrawal's avatar Urvashi Agrawal
Browse files

msm: kgsl: Set the CP_APRIV_CNTL for A650 



Prior to a650, packets like CP_INIT, SET_SECURE_MODE were executable
out of ringbuffer.From a650 onwards, these packets will be dropped by
CP if rbprivlevel bit is not set in CP_APRIV_CNTL.So set this bit
unconditionally so that CP doesn't drop these packets when it
sees them in the ringbuffer.

Change-Id: Ic29a17988d606b865389ca365eff69d51c73d594
Signed-off-by: default avatarUrvashi Agrawal <urvaagra@codeaurora.org>
parent f5f31790

drivers/gpu/msm/a6xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ 
#define A6XX_CP_SQE_INSTR_BASE_LO        0x830

#define A6XX_CP_SQE_INSTR_BASE_HI        0x831

#define A6XX_CP_MISC_CNTL                0x840

#define A6XX_CP_APRIV_CNTL               0X844

#define A6XX_CP_ROQ_THRESHOLDS_1         0x8C1

#define A6XX_CP_ROQ_THRESHOLDS_2         0x8C2

#define A6XX_CP_MEM_POOL_SIZE            0x8C3

drivers/gpu/msm/adreno_a6xx.c

+9 −0
Original line number Diff line number Diff line
@@ -1287,6 +1287,15 @@ static int a6xx_rb_start(struct adreno_device *adreno_dev, 
	if (ret)

		return ret;



	/*

	 * Set the RBPRIVLEVEL bit in this register to determine

	 * the privilege level of ucode executing packets in the RB,

	 * so we can come out of secure mode and CP does not drop

	 * the packet.

	 */

	if (adreno_is_a650(adreno_dev))

		kgsl_regwrite(device, A6XX_CP_APRIV_CNTL, (1 << 2));



	/* Clear the SQE_HALT to start the CP engine */

	kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1);