Merge branch 'linus' into perf/core, to pick up fixes (c69f203d) · Commits · e / devices / android_kernel_fairphone_FP4

Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt

+3 −3

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		@@ -45,7 +45,7 @@ The following clocks are available:
		- 1 15 SATA
		- 1 16 SATA USB
		- 1 17 Main
		- 1 18 SD/MMC
		- 1 18 SD/MMC/GOP
		- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
		- 1 22 USB3H0
		- 1 23 USB3H1
		@@ -65,7 +65,7 @@ Required properties:
		"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
		"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
		"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
		"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
		"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
		"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";

		Example:
		@@ -78,6 +78,6 @@ Example:
		gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
		"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
		"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
		"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
		"cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
		"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
		};

+0 −1

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		@@ -4,7 +4,6 @@ Required properties:
		- compatible: value should be one of the following
		"samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
		"samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
		"samsung,exynos4415-mipi-dsi" /* for Exynos4415 SoC */
		"samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
		"samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
		"samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */

+0 −1

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		@@ -11,7 +11,6 @@ Required properties:
		"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
		"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
		"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
		"samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
		"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
		"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */

+1 −1

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		@@ -13,7 +13,7 @@ Required Properties:
		- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
		before RK3288
		- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
		- "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
		- "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RV1108
		- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
		- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
		- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399

deleted100644 → 0

+0 −39

Original line number	Diff line number	Diff line
		Broadcom USB3 phy binding for northstar plus SoC
		The USB3 phy is internal to the SoC and is accessed using mdio interface.

		Required mdio bus properties:
		- reg: Should be 0x0 for SoC internal USB3 phy
		- #address-cells: must be 1
		- #size-cells: must be 0

		Required USB3 PHY properties:
		- compatible: should be "brcm,nsp-usb3-phy"
		- reg: USB3 Phy address on SoC internal MDIO bus and it should be 0x10.
		- usb3-ctrl-syscon: handler of syscon node defining physical address
		of usb3 control register.
		- #phy-cells: must be 0

		Required usb3 control properties:
		- compatible: should be "brcm,nsp-usb3-ctrl"
		- reg: offset and length of the control registers

		Example:

		mdio@0 {
		reg = <0x0>;
		#address-cells = <1>;
		#size-cells = <0>;

		usb3_phy: usb-phy@10 {
		compatible = "brcm,nsp-usb3-phy";
		reg = <0x10>;
		usb3-ctrl-syscon = <&usb3_ctrl>;
		#phy-cells = <0>;
		status = "disabled";
		};
		};

		usb3_ctrl: syscon@104408 {
		compatible = "brcm,nsp-usb3-ctrl", "syscon";
		reg = <0x104408 0x3fc>;
		};