Loading arch/arm64/boot/dts/qcom/lito-smp2p.dtsi 0 → 100644 +99 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> &soc { qcom,smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; mpss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; mpss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-npu { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <10>; npu_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; npu_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; }; arch/arm64/boot/dts/qcom/lito.dtsi +165 −0 Original line number Diff line number Diff line Loading @@ -968,12 +968,177 @@ interrupt-names = "l1-l2-faultirq", "l3-scu-faultirq"; }; tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "modem_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>, <&glink_cdsp>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 0x2>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "adsp_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_cdsp>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "dsps_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,cdsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_npu>; }; }; glink_npu: npu { qcom,remote-pid = <10>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "npu_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "npu"; qcom,glink-label = "npu"; qcom,npu_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,npu_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_cdsp>; }; }; }; qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>; reg-names = "msgram"; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "aop_qmp"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "aop"; qcom,early-boot; priority = <0>; mbox-desc-offset = <0x0>; #mbox-cells = <1>; }; }; #include "lito-pinctrl.dtsi" #include "lito-pm.dtsi" #include "lito-gdsc.dtsi" #include "lito-regulators.dtsi" #include "lito-smp2p.dtsi" &ufs_phy_gdsc { status = "ok"; Loading Loading
arch/arm64/boot/dts/qcom/lito-smp2p.dtsi 0 → 100644 +99 −0 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/soc/qcom,ipcc.h> &soc { qcom,smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <1>; mpss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; mpss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <2>; adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-cdsp { compatible = "qcom,smp2p"; qcom,smem = <94>, <432>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <5>; cdsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; cdsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; qcom,smp2p-npu { compatible = "qcom,smp2p"; qcom,smem = <617>, <616>; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; mboxes = <&ipcc_mproc IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>; qcom,local-pid = <0>; qcom,remote-pid = <10>; npu_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; npu_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; #interrupt-cells = <2>; }; }; };
arch/arm64/boot/dts/qcom/lito.dtsi +165 −0 Original line number Diff line number Diff line Loading @@ -968,12 +968,177 @@ interrupt-names = "l1-l2-faultirq", "l3-scu-faultirq"; }; tcsr_mutex_block: syscon@1f40000 { compatible = "syscon"; reg = <0x1f40000 0x20000>; }; tcsr_mutex: hwlock { compatible = "qcom,tcsr-mutex"; syscon = <&tcsr_mutex_block 0 0x1000>; #hwlock-cells = <1>; }; smem: qcom,smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; hwlocks = <&tcsr_mutex 3>; }; qcom,glink { compatible = "qcom,glink"; #address-cells = <1>; #size-cells = <1>; ranges; glink_modem: modem { qcom,remote-pid = <1>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "modem_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "modem"; qcom,glink-label = "mpss"; qcom,modem_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,modem_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>, <&glink_cdsp>; }; qcom,msm_fastrpc_rpmsg { compatible = "qcom,msm-fastrpc-rpmsg"; qcom,glink-channels = "fastrpcglink-apps-dsp"; qcom,intents = <0x64 64>; }; qcom,modem_ds { qcom,glink-channels = "DS"; qcom,intents = <0x4000 0x2>; }; }; glink_adsp: adsp { qcom,remote-pid = <2>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "adsp_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "adsp"; qcom,glink-label = "lpass"; qcom,adsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,adsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_cdsp>; }; }; glink_cdsp: cdsp { qcom,remote-pid = <5>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "dsps_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "cdsp"; qcom,glink-label = "cdsp"; qcom,cdsp_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,cdsp_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_npu>; }; }; glink_npu: npu { qcom,remote-pid = <10>; transport = "smem"; mboxes = <&ipcc_mproc IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "npu_smem"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "npu"; qcom,glink-label = "npu"; qcom,npu_qrtr { qcom,glink-channels = "IPCRTR"; qcom,intents = <0x800 5 0x2000 3 0x4400 2>; }; qcom,npu_glink_ssr { qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_modem>, <&glink_adsp>, <&glink_cdsp>; }; }; }; qmp_aop: qcom,qmp-aop@c300000 { compatible = "qcom,qmp-mbox"; reg = <0xc300000 0x1000>; reg-names = "msgram"; mboxes = <&ipcc_mproc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; mbox-names = "aop_qmp"; interrupt-parent = <&ipcc_mproc>; interrupts = <IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; label = "aop"; qcom,early-boot; priority = <0>; mbox-desc-offset = <0x0>; #mbox-cells = <1>; }; }; #include "lito-pinctrl.dtsi" #include "lito-pm.dtsi" #include "lito-gdsc.dtsi" #include "lito-regulators.dtsi" #include "lito-smp2p.dtsi" &ufs_phy_gdsc { status = "ok"; Loading