Loading drivers/clk/qcom/mdss/mdss-dsi-pll-28nm-util.c +5 −0 Original line number Diff line number Diff line Loading @@ -590,6 +590,7 @@ unsigned long vco_28nm_recalc_rate(struct clk_hw *hw, if (dsi_pll_lock_status(rsc)) { rsc->handoff_resources = true; rsc->cont_splash_enabled = true; rsc->pll_on = true; vco_rate = vco_get_rate(vco); } else { Loading Loading @@ -629,6 +630,10 @@ int vco_28nm_prepare(struct clk_hw *hw) MDSS_PLL_REG_W(rsc->pll_base, DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, rsc->cached_vreg_cfg); } else if (!rsc->handoff_resources && rsc->cont_splash_enabled) { MDSS_PLL_REG_W(rsc->pll_base, DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, rsc->cached_vreg_cfg); } rc = dsi_pll_enable(vco); Loading drivers/clk/qcom/mdss/mdss-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -146,6 +146,7 @@ struct mdss_pll_resources { * feature is disabled. */ bool handoff_resources; bool cont_splash_enabled; /* * caching the pll trim codes in the case of dynamic refresh Loading Loading
drivers/clk/qcom/mdss/mdss-dsi-pll-28nm-util.c +5 −0 Original line number Diff line number Diff line Loading @@ -590,6 +590,7 @@ unsigned long vco_28nm_recalc_rate(struct clk_hw *hw, if (dsi_pll_lock_status(rsc)) { rsc->handoff_resources = true; rsc->cont_splash_enabled = true; rsc->pll_on = true; vco_rate = vco_get_rate(vco); } else { Loading Loading @@ -629,6 +630,10 @@ int vco_28nm_prepare(struct clk_hw *hw) MDSS_PLL_REG_W(rsc->pll_base, DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, rsc->cached_vreg_cfg); } else if (!rsc->handoff_resources && rsc->cont_splash_enabled) { MDSS_PLL_REG_W(rsc->pll_base, DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG, rsc->cached_vreg_cfg); } rc = dsi_pll_enable(vco); Loading
drivers/clk/qcom/mdss/mdss-pll.h +1 −0 Original line number Diff line number Diff line Loading @@ -146,6 +146,7 @@ struct mdss_pll_resources { * feature is disabled. */ bool handoff_resources; bool cont_splash_enabled; /* * caching the pll trim codes in the case of dynamic refresh Loading