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Commit c5a38ae8 authored by Kim Phillips's avatar Kim Phillips Committed by Greg Kroah-Hartman
Browse files

perf/x86/amd/ibs: Fix raw sample data accumulation 



commit 36e1be8ada994d509538b3b1d0af8b63c351e729 upstream.

Neither IbsBrTarget nor OPDATA4 are populated in IBS Fetch mode.
Don't accumulate them into raw sample user data in that case.

Also, in Fetch mode, add saving the IBS Fetch Control Extended MSR.

Technically, there is an ABI change here with respect to the IBS raw
sample data format, but I don't see any perf driver version information
being included in perf.data file headers, but, existing users can detect
whether the size of the sample record has reduced by 8 bytes to
determine whether the IBS driver has this fix.

Fixes: 904cb367 ("perf/x86/amd/ibs: Update IBS MSRs and feature definitions")
Reported-by: default avatarStephane Eranian <stephane.eranian@google.com>
Signed-off-by: default avatarKim Phillips <kim.phillips@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20200908214740.18097-6-kim.phillips@amd.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a1c59cb6

arch/x86/events/amd/ibs.c

+16 −10
Original line number Diff line number Diff line
@@ -647,12 +647,13 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
				       perf_ibs->offset_max,

				       offset + 1);

	} while (offset < offset_max);

	if (event->attr.sample_type & PERF_SAMPLE_RAW) {

	/*

		 * Read IbsBrTarget and IbsOpData4 separately

	 * Read IbsBrTarget, IbsOpData4, and IbsExtdCtl separately

	 * depending on their availability.

	 * Can't add to offset_max as they are staggered

	 */

	if (event->attr.sample_type & PERF_SAMPLE_RAW) {

		if (perf_ibs == &perf_ibs_op) {

			if (ibs_caps & IBS_CAPS_BRNTRGT) {

				rdmsrl(MSR_AMD64_IBSBRTARGET, *buf++);

				size++;
@@ -662,6 +663,11 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 
				size++;

			}

		}

		if (perf_ibs == &perf_ibs_fetch && (ibs_caps & IBS_CAPS_FETCHCTLEXTD)) {

			rdmsrl(MSR_AMD64_ICIBSEXTDCTL, *buf++);

			size++;

		}

	}

	ibs_data.size = sizeof(u64) * size;



	regs = *iregs;

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -377,6 +377,7 @@ 
#define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)

#define MSR_AMD64_IBSCTL		0xc001103a

#define MSR_AMD64_IBSBRTARGET		0xc001103b

#define MSR_AMD64_ICIBSEXTDCTL		0xc001103c

#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */

#define MSR_AMD64_SEV			0xc0010131