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Commit c55fbcb8 authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Kishon Vijay Abraham I
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dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate 



Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs

Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 8833ebf4

Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

+4 −0
Original line number Diff line number Diff line
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node): 
 - reg		: offset and length of register shared by multiple ports,

		  exclude port's private register. It is needed on mt2701

		  and mt8173, but not on mt2712.

 - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate

		  calibrate

 - mediatek,src-coef	: coefficient for slew rate calibrate, depends on

		  SoC process



Required properties (port (child) node):

- reg		: address and length of the register set for the port.