Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c51f7167 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel into drm-next 

- fbc improvements when stolen memory is tight (Ben)
- cdclk handling improvements for vlv/chv (Ville)
- proper fix for stuck primary planes on gmch platforms with cxsr (Imre&Ebgert
  Eich)
- gen8 hw semaphore support (Ben)
- more execlist prep work from Oscar Mateo
- locking fixes for primary planes (Matt Roper)
- code rework to support runtime pm for dpms on hsw/bdw (Paulo, Imre & me), but
  not yet enabled because some fixes from Paulo haven't made the cut
- more gpu boost tuning from Chris
- as usual piles of little things all over

* tag 'drm-intel-next-2014-07-11' of git://anongit.freedesktop.org/drm-intel: (93 commits)
  drm/i915: Make the RPS interrupt generation mask handle the vlv wa
  drm/i915: Move RPS evaluation interval counters to i915->rps
  drm/i915: Don't cast a pointer to void* unnecessarily
  drm/i915: don't read LVDS regs at compute_config time
  drm/i915: check the power domains in intel_lvds_get_hw_state()
  drm/i915: check the power domains in ironlake_get_pipe_config()
  drm/i915: don't skip shared DPLL assertion on LPT
  drm/i915: Only touch WRPLL hw state in enable/disable hooks
  drm/i915: Switch to common shared dpll framework for WRPLLs
  drm/i915: ->enable hook for WRPLLs
  drm/i915: ->disable hook for WRPLLs
  drm/i915: State readout support for WRPLLs
  drm/i915: add POWER_DOMAIN_PLLS
  drm/i915: Document that the pll->mode_set hook is optional
  drm/i915: Basic shared dpll support for WRPLLs
  drm/i915: Precompute static ddi_pll_sel values in encoders
  drm/i915: BDW also has special-purpose DP DDI clocks
  drm/i915: State readout and cross-checking for ddi_pll_sel
  drm/i915: Move ddi_pll_sel into the pipe config
  drm/i915: Add a debugfs file for the shared dpll state
  ...
parents b957f457 7b3c29f6

drivers/gpu/drm/i915/i915_debugfs.c

+183 −118
Original line number Diff line number Diff line
@@ -176,7 +176,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 


static void describe_ctx(struct seq_file *m, struct intel_context *ctx)

{

	seq_putc(m, ctx->is_initialized ? 'I' : 'i');

	seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');

	seq_putc(m, ctx->remap_slice ? 'R' : 'r');

	seq_putc(m, ' ');

}
@@ -994,29 +994,6 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops, 
			i915_next_seqno_get, i915_next_seqno_set,

			"0x%llx\n");



static int i915_rstdby_delays(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u16 crstanddelay;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	crstanddelay = I915_READ16(CRSTANDVID);



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));



	return 0;

}



static int i915_frequency_info(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;
@@ -1158,61 +1135,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
	return ret;

}



static int i915_delayfreq_table(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 delayfreq;

	int ret, i;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	for (i = 0; i < 16; i++) {

		delayfreq = I915_READ(PXVFREQ_BASE + i * 4);

		seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,

			   (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);

	}



	intel_runtime_pm_put(dev_priv);



	mutex_unlock(&dev->struct_mutex);



	return 0;

}



static inline int MAP_TO_MV(int map)

{

	return 1250 - (map * 25);

}



static int i915_inttoext_table(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 inttoext;

	int ret, i;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	for (i = 1; i <= 32; i++) {

		inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);

		seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);

	}



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);



	return 0;

}



static int ironlake_drpc_info(struct seq_file *m)

{

	struct drm_info_node *node = m->private;
@@ -1523,10 +1445,17 @@ static int i915_ips_status(struct seq_file *m, void *unused) 


	intel_runtime_pm_get(dev_priv);



	if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)

		seq_puts(m, "enabled\n");

	seq_printf(m, "Enabled by kernel parameter: %s\n",

		   yesno(i915.enable_ips));



	if (INTEL_INFO(dev)->gen >= 8) {

		seq_puts(m, "Currently: unknown\n");

	} else {

		if (I915_READ(IPS_CTL) & IPS_ENABLE)

			seq_puts(m, "Currently: enabled\n");

		else

		seq_puts(m, "disabled\n");

			seq_puts(m, "Currently: disabled\n");

	}



	intel_runtime_pm_put(dev_priv);
@@ -1630,26 +1559,6 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) 
	return ret;

}



static int i915_gfxec(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));

	intel_runtime_pm_put(dev_priv);



	mutex_unlock(&dev->struct_mutex);



	return 0;

}



static int i915_opregion(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = m->private;
@@ -1746,7 +1655,7 @@ static int i915_context_status(struct seq_file *m, void *unused) 
	}



	list_for_each_entry(ctx, &dev_priv->context_list, link) {

		if (ctx->obj == NULL)

		if (ctx->legacy_hw_ctx.rcs_state == NULL)

			continue;



		seq_puts(m, "HW context ");
@@ -1755,7 +1664,7 @@ static int i915_context_status(struct seq_file *m, void *unused) 
			if (ring->default_context == ctx)

				seq_printf(m, "(default context %s) ", ring->name);



		describe_obj(m, ctx->obj);

		describe_obj(m, ctx->legacy_hw_ctx.rcs_state);

		seq_putc(m, '\n');

	}
@@ -1869,7 +1778,7 @@ static int per_file_ctx(int id, void *ptr, void *data) 
	if (i915_gem_context_is_default(ctx))

		seq_puts(m, "  default context:\n");

	else

		seq_printf(m, "  context %d:\n", ctx->id);

		seq_printf(m, "  context %d:\n", ctx->user_handle);

	ppgtt->debug_dump(ppgtt, m);



	return 0;
@@ -2134,6 +2043,8 @@ static const char *power_domain_str(enum intel_display_power_domain domain) 
		return "VGA";

	case POWER_DOMAIN_AUDIO:

		return "AUDIO";

	case POWER_DOMAIN_PLLS:

		return "PLLS";

	case POWER_DOMAIN_INIT:

		return "INIT";

	default:
@@ -2358,17 +2269,17 @@ static int i915_display_info(struct seq_file *m, void *unused) 
		bool active;

		int x, y;



		seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",

		seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",

			   crtc->base.base.id, pipe_name(crtc->pipe),

			   yesno(crtc->active));

			   yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);

		if (crtc->active) {

			intel_crtc_info(m, crtc);



			active = cursor_position(dev, crtc->pipe, &x, &y);

			seq_printf(m, "\tcursor visible? %s, position (%d, %d), addr 0x%08x, active? %s\n",

			seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",

				   yesno(crtc->cursor_base),

				   x, y, crtc->cursor_addr,

				   yesno(active));

				   x, y, crtc->cursor_width, crtc->cursor_height,

				   crtc->cursor_addr, yesno(active));

		}



		seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
@@ -2388,6 +2299,104 @@ static int i915_display_info(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_semaphore_status(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *ring;

	int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);

	int i, j, ret;



	if (!i915_semaphore_is_enabled(dev)) {

		seq_puts(m, "Semaphores are disabled\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;

	intel_runtime_pm_get(dev_priv);



	if (IS_BROADWELL(dev)) {

		struct page *page;

		uint64_t *seqno;



		page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);



		seqno = (uint64_t *)kmap_atomic(page);

		for_each_ring(ring, dev_priv, i) {

			uint64_t offset;



			seq_printf(m, "%s\n", ring->name);



			seq_puts(m, "  Last signal:");

			for (j = 0; j < num_rings; j++) {

				offset = i * I915_NUM_RINGS + j;

				seq_printf(m, "0x%08llx (0x%02llx) ",

					   seqno[offset], offset * 8);

			}

			seq_putc(m, '\n');



			seq_puts(m, "  Last wait:  ");

			for (j = 0; j < num_rings; j++) {

				offset = i + (j * I915_NUM_RINGS);

				seq_printf(m, "0x%08llx (0x%02llx) ",

					   seqno[offset], offset * 8);

			}

			seq_putc(m, '\n');



		}

		kunmap_atomic(seqno);

	} else {

		seq_puts(m, "  Last signal:");

		for_each_ring(ring, dev_priv, i)

			for (j = 0; j < num_rings; j++)

				seq_printf(m, "0x%08x\n",

					   I915_READ(ring->semaphore.mbox.signal[j]));

		seq_putc(m, '\n');

	}



	seq_puts(m, "\nSync seqno:\n");

	for_each_ring(ring, dev_priv, i) {

		for (j = 0; j < num_rings; j++) {

			seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);

		}

		seq_putc(m, '\n');

	}

	seq_putc(m, '\n');



	intel_runtime_pm_put(dev_priv);

	mutex_unlock(&dev->struct_mutex);

	return 0;

}



static int i915_shared_dplls_info(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	int i;



	drm_modeset_lock_all(dev);

	for (i = 0; i < dev_priv->num_shared_dpll; i++) {

		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];



		seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);

		seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,

			   pll->active, yesno(pll->on));

		seq_printf(m, " tracked hardware state:\n");

		seq_printf(m, " dpll:    0x%08x\n", pll->hw_state.dpll);

		seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);

		seq_printf(m, " fp0:     0x%08x\n", pll->hw_state.fp0);

		seq_printf(m, " fp1:     0x%08x\n", pll->hw_state.fp1);

		seq_printf(m, " wrpll:   0x%08x\n", pll->hw_state.wrpll);

	}

	drm_modeset_unlock_all(dev);



	return 0;

}



struct pipe_crc_info {

	const char *name;

	struct drm_device *dev;
@@ -2860,7 +2869,60 @@ static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 
	return 0;

}



static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,

static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *crtc =

		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);



	drm_modeset_lock_all(dev);

	/*

	 * If we use the eDP transcoder we need to make sure that we don't

	 * bypass the pfit, since otherwise the pipe CRC source won't work. Only

	 * relevant on hsw with pipe A when using the always-on power well

	 * routing.

	 */

	if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&

	    !crtc->config.pch_pfit.enabled) {

		crtc->config.pch_pfit.force_thru = true;



		intel_display_power_get(dev_priv,

					POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));



		dev_priv->display.crtc_disable(&crtc->base);

		dev_priv->display.crtc_enable(&crtc->base);

	}

	drm_modeset_unlock_all(dev);

}



static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_crtc *crtc =

		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);



	drm_modeset_lock_all(dev);

	/*

	 * If we use the eDP transcoder we need to make sure that we don't

	 * bypass the pfit, since otherwise the pipe CRC source won't work. Only

	 * relevant on hsw with pipe A when using the always-on power well

	 * routing.

	 */

	if (crtc->config.pch_pfit.force_thru) {

		crtc->config.pch_pfit.force_thru = false;



		dev_priv->display.crtc_disable(&crtc->base);

		dev_priv->display.crtc_enable(&crtc->base);



		intel_display_power_put(dev_priv,

					POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));

	}

	drm_modeset_unlock_all(dev);

}



static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,

				enum pipe pipe,

				enum intel_pipe_crc_source *source,

				uint32_t *val)

{

	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
@@ -2874,6 +2936,9 @@ static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, 
		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;

		break;

	case INTEL_PIPE_CRC_SOURCE_PF:

		if (IS_HASWELL(dev) && pipe == PIPE_A)

			hsw_trans_edp_pipe_A_crc_wa(dev);



		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;

		break;

	case INTEL_PIPE_CRC_SOURCE_NONE:
@@ -2910,7 +2975,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
	else if (IS_GEN5(dev) || IS_GEN6(dev))

		ret = ilk_pipe_crc_ctl_reg(&source, &val);

	else

		ret = ivb_pipe_crc_ctl_reg(&source, &val);

		ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);



	if (ret != 0)

		return ret;
@@ -2962,6 +3027,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe, 
			g4x_undo_pipe_scramble_reset(dev, pipe);

		else if (IS_VALLEYVIEW(dev))

			vlv_undo_pipe_scramble_reset(dev, pipe);

		else if (IS_HASWELL(dev) && pipe == PIPE_A)

			hsw_undo_trans_edp_pipe_A_crc_wa(dev);

	}



	return 0;
@@ -3815,14 +3882,10 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},

	{"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},

	{"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},

	{"i915_rstdby_delays", i915_rstdby_delays, 0},

	{"i915_frequency_info", i915_frequency_info, 0},

	{"i915_delayfreq_table", i915_delayfreq_table, 0},

	{"i915_inttoext_table", i915_inttoext_table, 0},

	{"i915_drpc_info", i915_drpc_info, 0},

	{"i915_emon_status", i915_emon_status, 0},

	{"i915_ring_freq_table", i915_ring_freq_table, 0},

	{"i915_gfxec", i915_gfxec, 0},

	{"i915_fbc_status", i915_fbc_status, 0},

	{"i915_ips_status", i915_ips_status, 0},

	{"i915_sr_status", i915_sr_status, 0},
@@ -3839,6 +3902,8 @@ static const struct drm_info_list i915_debugfs_list[] = { 
	{"i915_pc8_status", i915_pc8_status, 0},

	{"i915_power_domain_info", i915_power_domain_info, 0},

	{"i915_display_info", i915_display_info, 0},

	{"i915_semaphore_status", i915_semaphore_status, 0},

	{"i915_shared_dplls_info", i915_shared_dplls_info, 0},

};

#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)

drivers/gpu/drm/i915/i915_dma.c

+4 −4
Original line number Diff line number Diff line
@@ -1593,7 +1593,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (dev_priv == NULL)

		return -ENOMEM;



	dev->dev_private = (void *)dev_priv;

	dev->dev_private = dev_priv;

	dev_priv->dev = dev;



	/* copy initial configuration to dev_priv->info */
@@ -1954,11 +1954,11 @@ void i915_driver_lastclose(struct drm_device *dev) 
	i915_dma_cleanup(dev);

}



void i915_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)

void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)

{

	mutex_lock(&dev->struct_mutex);

	i915_gem_context_close(dev, file_priv);

	i915_gem_release(dev, file_priv);

	i915_gem_context_close(dev, file);

	i915_gem_release(dev, file);

	mutex_unlock(&dev->struct_mutex);

}

drivers/gpu/drm/i915/i915_drv.c

+6 −7
Original line number Diff line number Diff line
@@ -477,10 +477,6 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) 
	if (i915.semaphores >= 0)

		return i915.semaphores;



	/* Until we get further testing... */

	if (IS_GEN8(dev))

		return false;



#ifdef CONFIG_INTEL_IOMMU

	/* Enable semaphores on SNB when IO remapping is off */

	if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
@@ -520,6 +516,8 @@ static int i915_drm_freeze(struct drm_device *dev) 
			return error;

		}



		flush_delayed_work(&dev_priv->rps.delayed_resume_work);



		intel_runtime_pm_disable_interrupts(dev);



		intel_suspend_gt_powersave(dev);
@@ -541,10 +539,11 @@ static int i915_drm_freeze(struct drm_device *dev) 


	i915_save_state(dev);



	if (acpi_target_system_state() >= ACPI_STATE_S3)

	opregion_target_state = PCI_D3cold;

	else

#if IS_ENABLED(CONFIG_ACPI_SLEEP)

	if (acpi_target_system_state() < ACPI_STATE_S3)

		opregion_target_state = PCI_D1;

#endif

	intel_opregion_notify_adapter(dev, opregion_target_state);



	intel_uncore_forcewake_reset(dev, false);

drivers/gpu/drm/i915/i915_drv.h

+59 −19
Original line number Diff line number Diff line
@@ -129,6 +129,7 @@ enum intel_display_power_domain { 
	POWER_DOMAIN_PORT_OTHER,

	POWER_DOMAIN_VGA,

	POWER_DOMAIN_AUDIO,

	POWER_DOMAIN_PLLS,

	POWER_DOMAIN_INIT,



	POWER_DOMAIN_NUM,
@@ -184,8 +185,10 @@ struct i915_mmu_object; 
enum intel_dpll_id {

	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */

	/* real shared dpll ids must be >= 0 */

	DPLL_ID_PCH_PLL_A,

	DPLL_ID_PCH_PLL_B,

	DPLL_ID_PCH_PLL_A = 0,

	DPLL_ID_PCH_PLL_B = 1,

	DPLL_ID_WRPLL1 = 0,

	DPLL_ID_WRPLL2 = 1,

};

#define I915_NUM_PLLS 2
@@ -194,6 +197,7 @@ struct intel_dpll_hw_state { 
	uint32_t dpll_md;

	uint32_t fp0;

	uint32_t fp1;

	uint32_t wrpll;

};



struct intel_shared_dpll {
@@ -204,6 +208,8 @@ struct intel_shared_dpll { 
	/* should match the index in the dev_priv->shared_dplls array */

	enum intel_dpll_id id;

	struct intel_dpll_hw_state hw_state;

	/* The mode_set hook is optional and should be used together with the

	 * intel_prepare_shared_dpll function. */

	void (*mode_set)(struct drm_i915_private *dev_priv,

			 struct intel_shared_dpll *pll);

	void (*enable)(struct drm_i915_private *dev_priv,
@@ -228,12 +234,6 @@ void intel_link_compute_m_n(int bpp, int nlanes, 
			    int pixel_clock, int link_clock,

			    struct intel_link_m_n *m_n);



struct intel_ddi_plls {

	int spll_refcount;

	int wrpll1_refcount;

	int wrpll2_refcount;

};



/* Interface history:

 *

 * 1.1: Original.
@@ -324,6 +324,7 @@ struct drm_i915_error_state { 
	u64 fence[I915_MAX_NUM_FENCES];

	struct intel_overlay_error_state *overlay;

	struct intel_display_error_state *display;

	struct drm_i915_error_object *semaphore_obj;



	struct drm_i915_error_ring {

		bool valid;
@@ -584,27 +585,48 @@ struct i915_ctx_hang_stats { 
};



/* This must match up with the value previously used for execbuf2.rsvd1. */

#define DEFAULT_CONTEXT_ID 0

#define DEFAULT_CONTEXT_HANDLE 0

/**

 * struct intel_context - as the name implies, represents a context.

 * @ref: reference count.

 * @user_handle: userspace tracking identity for this context.

 * @remap_slice: l3 row remapping information.

 * @file_priv: filp associated with this context (NULL for global default

 *	       context).

 * @hang_stats: information about the role of this context in possible GPU

 *		hangs.

 * @vm: virtual memory space used by this context.

 * @legacy_hw_ctx: render context backing object and whether it is correctly

 *                initialized (legacy ring submission mechanism only).

 * @link: link in the global list of contexts.

 *

 * Contexts are memory images used by the hardware to store copies of their

 * internal state.

 */

struct intel_context {

	struct kref ref;

	int id;

	bool is_initialized;

	int user_handle;

	uint8_t remap_slice;

	struct drm_i915_file_private *file_priv;

	struct drm_i915_gem_object *obj;

	struct i915_ctx_hang_stats hang_stats;

	struct i915_address_space *vm;



	struct {

		struct drm_i915_gem_object *rcs_state;

		bool initialized;

	} legacy_hw_ctx;



	struct list_head link;

};



struct i915_fbc {

	unsigned long size;

	unsigned threshold;

	unsigned int fb_id;

	enum plane plane;

	int y;



	struct drm_mm_node *compressed_fb;

	struct drm_mm_node compressed_fb;

	struct drm_mm_node *compressed_llb;



	struct intel_fbc_work {
@@ -880,6 +902,12 @@ struct vlv_s0ix_state { 
	u32 clock_gate_dis2;

};



struct intel_rps_ei {

	u32 cz_clock;

	u32 render_c0;

	u32 media_c0;

};



struct intel_gen6_power_mgmt {

	/* work and pm_iir are protected by dev_priv->irq_lock */

	struct work_struct work;
@@ -904,12 +932,17 @@ struct intel_gen6_power_mgmt { 
	u8 rp1_freq;		/* "less than" RP0 power/freqency */

	u8 rp0_freq;		/* Non-overclocked max frequency. */



	u32 ei_interrupt_count;



	int last_adj;

	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;



	bool enabled;

	struct delayed_work delayed_resume_work;



	/* manual wa residency calculations */

	struct intel_rps_ei up_ei, down_ei;



	/*

	 * Protects RPS/RC6 register access and PCU communication.

	 * Must be taken after struct_mutex if nested.
@@ -1374,6 +1407,7 @@ struct drm_i915_private { 


	struct pci_dev *bridge_dev;

	struct intel_engine_cs ring[I915_NUM_RINGS];

	struct drm_i915_gem_object *semaphore_obj;

	uint32_t last_seqno, next_seqno;



	drm_dma_handle_t *status_page_dmah;
@@ -1480,7 +1514,6 @@ struct drm_i915_private { 


	int num_shared_dpll;

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

	struct intel_ddi_plls ddi_plls;

	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];



	/* Reclocking support */
@@ -1557,6 +1590,11 @@ struct drm_i915_private { 


	struct i915_runtime_pm pm;



	struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];

	u32 long_hpd_port_mask;

	u32 short_hpd_port_mask;

	struct work_struct dig_port_work;



	/* Old dri1 support infrastructure, beware the dragons ya fools entering

	 * here! */

	struct i915_dri1_state dri1;
@@ -2097,12 +2135,12 @@ void i915_update_dri1_breadcrumb(struct drm_device *dev); 
extern void i915_kernel_lost_context(struct drm_device * dev);

extern int i915_driver_load(struct drm_device *, unsigned long flags);

extern int i915_driver_unload(struct drm_device *);

extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);

extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);

extern void i915_driver_lastclose(struct drm_device * dev);

extern void i915_driver_preclose(struct drm_device *dev,

				 struct drm_file *file_priv);

				 struct drm_file *file);

extern void i915_driver_postclose(struct drm_device *dev,

				  struct drm_file *file_priv);

				  struct drm_file *file);

extern int i915_driver_device_is_agp(struct drm_device * dev);

#ifdef CONFIG_COMPAT

extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
@@ -2457,7 +2495,7 @@ static inline void i915_gem_context_unreference(struct intel_context *ctx) 


static inline bool i915_gem_context_is_default(const struct intel_context *c)

{

	return c->id == DEFAULT_CONTEXT_ID;

	return c->user_handle == DEFAULT_CONTEXT_HANDLE;

}



int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
@@ -2488,7 +2526,7 @@ static inline void i915_gem_chipset_flush(struct drm_device *dev) 


/* i915_gem_stolen.c */

int i915_gem_init_stolen(struct drm_device *dev);

int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);

int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);

void i915_gem_stolen_cleanup_compression(struct drm_device *dev);

void i915_gem_cleanup_stolen(struct drm_device *dev);

struct drm_i915_gem_object *
@@ -2647,6 +2685,8 @@ extern void gen6_set_rps(struct drm_device *dev, u8 val); 
extern void valleyview_set_rps(struct drm_device *dev, u8 val);

extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);

extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);

extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,

				  bool enable);

extern void intel_detect_pch(struct drm_device *dev);

extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);

extern int intel_enable_rc6(const struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+5 −3
Original line number Diff line number Diff line
@@ -1168,7 +1168,7 @@ static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno, 


	timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;



	if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {

	if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {

		gen6_rps_boost(dev_priv);

		if (file_priv)

			mod_delayed_work(dev_priv->wq,
@@ -2330,7 +2330,7 @@ int __i915_add_request(struct intel_engine_cs *ring, 
	u32 request_ring_position, request_start;

	int ret;



	request_start = intel_ring_get_tail(ring);

	request_start = intel_ring_get_tail(ring->buffer);

	/*

	 * Emit any outstanding flushes - execbuf can fail to emit the flush

	 * after having emitted the batchbuffer command. Hence we need to fix
@@ -2351,7 +2351,7 @@ int __i915_add_request(struct intel_engine_cs *ring, 
	 * GPU processing the request, we never over-estimate the

	 * position of the head.

	 */

	request_ring_position = intel_ring_get_tail(ring);

	request_ring_position = intel_ring_get_tail(ring->buffer);



	ret = ring->add_request(ring);

	if (ret)
@@ -2842,6 +2842,8 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, 
	idx = intel_ring_sync_index(from, to);



	seqno = obj->last_read_seqno;

	/* Optimization: Avoid semaphore sync when we are sure we already

	 * waited for an object with higher seqno */

	if (seqno <= from->semaphore.sync_seqno[idx])

		return 0;