Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c51e078f authored by Marcelo Tosatti's avatar Marcelo Tosatti Committed by Paul Mackerras
Browse files

[PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation 



Instantiation of 8MB pages on the TLB cache for the kernel static
mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations.
This ensures r3 gets saved and restored.

Signed-off-by: default avatarMarcelo Tosatti <marcelo@kvack.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent e4de0021

arch/ppc/kernel/head_8xx.S

+0 −4
Original line number Diff line number Diff line
@@ -355,9 +355,7 @@ InstructionTLBMiss: 


	. = 0x1200

DataStoreTLBMiss:

#ifdef CONFIG_8xx_CPU6

	stw	r3, 8(r0)

#endif

	DO_8xx_CPU6(0x3f80, r3)

	mtspr	SPRN_M_TW, r10	/* Save a couple of working registers */

	mfcr	r10
@@ -417,9 +415,7 @@ DataStoreTLBMiss: 
	lwz	r11, 0(r0)

	mtcr	r11

	lwz	r11, 4(r0)

#ifdef CONFIG_8xx_CPU6

	lwz	r3, 8(r0)

#endif

	rfi



/* This is an instruction TLB error on the MPC8xx.  This could be due