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Commit c50fc262 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller
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Documentation: dtb: xgene: Add rxlos GPIO mapping

parent 72d25643
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+3 −0
Original line number Original line Diff line number Diff line
@@ -47,6 +47,9 @@ Optional properties:
	    Valid values are between 0 to 7, that maps to
	    Valid values are between 0 to 7, that maps to
	    273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
	    273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
	    Default value is 2, which corresponds to 899 ps
	    Default value is 2, which corresponds to 899 ps
- rxlos-gpios: Input gpio from SFP+ module to indicate availability of
	       incoming signal.



Example:
Example:
	menetclk: menetclk {
	menetclk: menetclk {