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Commit c4d3ae68 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Consolidate checks for memcpy-from-wc support 



In order to silence sparse:

../drivers/gpu/drm/i915/i915_gpu_error.c:200:39: warning: Using plain integer as NULL pointer

add a helper to check whether we have sse4.1 and that the desired
alignment is valid for acceleration.

v2: Explain the macros and split the two use cases between
i915_has_memcpy_from_wc() and i915_can_memcpy_from_wc().

Reported-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170106152013.24684-1-chris@chris-wilson.co.uk
parent 7ec73b7e

drivers/gpu/drm/i915/i915_cmd_parser.c

+1 −1
Original line number Diff line number Diff line
@@ -1079,7 +1079,7 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 


	src = ERR_PTR(-ENODEV);

	if (src_needs_clflush &&

	    i915_memcpy_from_wc((void *)(uintptr_t)batch_start_offset, NULL, 0)) {

	    i915_can_memcpy_from_wc(NULL, batch_start_offset, 0)) {

		src = i915_gem_object_pin_map(src_obj, I915_MAP_WC);

		if (!IS_ERR(src)) {

			i915_memcpy_from_wc(dst,

drivers/gpu/drm/i915/i915_drv.h

+16 −0
Original line number Diff line number Diff line
@@ -4021,6 +4021,22 @@ __i915_request_irq_complete(struct drm_i915_gem_request *req) 
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);

bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);



/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,

 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot

 * perform the operation. To check beforehand, pass in the parameters to

 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,

 * you only need to pass in the minor offsets, page-aligned pointers are

 * always valid.

 *

 * For just checking for SSE4.1, in the foreknowledge that the future use

 * will be correctly aligned, just use i915_has_memcpy_from_wc().

 */

#define i915_can_memcpy_from_wc(dst, src, len) \

	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)



#define i915_has_memcpy_from_wc() \

	i915_memcpy_from_wc(NULL, NULL, 0)



/* i915_mm.c */

int remap_io_mapping(struct vm_area_struct *vma,

		     unsigned long addr, unsigned long pfn, unsigned long size,

drivers/gpu/drm/i915/i915_gpu_error.c

+1 −1
Original line number Diff line number Diff line
@@ -197,7 +197,7 @@ static bool compress_init(struct compress *c) 
	}



	c->tmp = NULL;

	if (i915_memcpy_from_wc(NULL, 0, 0))

	if (i915_has_memcpy_from_wc())

		c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);



	return true;

drivers/gpu/drm/i915/i915_guc_submission.c

+1 −1
Original line number Diff line number Diff line
@@ -1197,7 +1197,7 @@ static void guc_log_create(struct intel_guc *guc) 
		 * it should be present on the chipsets supporting GuC based

		 * submisssions.

		 */

		if (WARN_ON(!i915_memcpy_from_wc(NULL, NULL, 0))) {

		if (WARN_ON(!i915_has_memcpy_from_wc())) {

			/* logging will not be enabled */

			i915.guc_log_level = -1;

			return;