drm/sun4i: hdmi: Add A31 specific DDC register definitions

#define SUN4I_HDMI_DDC_FIFO_SIZE	16

/* A31 specific */

#define SUN6I_HDMI_DDC_CTRL_REG		0x500

#define SUN6I_HDMI_DDC_CTRL_RESET		BIT(31)

#define SUN6I_HDMI_DDC_CTRL_START_CMD		BIT(27)

#define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE		BIT(6)

#define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE		BIT(4)

#define SUN6I_HDMI_DDC_CTRL_ENABLE		BIT(0)

#define SUN6I_HDMI_DDC_CMD_REG		0x508

#define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count)	((count) << 16)

/* command types in lower 3 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_ADDR_REG		0x50c

#define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg)	(((seg) & 0xff) << 24)

#define SUN6I_HDMI_DDC_ADDR_EDDC(addr)		(((addr) & 0xff) << 16)

#define SUN6I_HDMI_DDC_ADDR_OFFSET(off)		(((off) & 0xff) << 8)

#define SUN6I_HDMI_DDC_ADDR_SLAVE(addr)		(((addr) & 0xff) << 1)

#define SUN6I_HDMI_DDC_INT_STATUS_REG	0x514

#define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT	BIT(8)

/* lower 8 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_FIFO_CTRL_REG	0x518

#define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR		BIT(15)

/* lower 9 bits are the same as sun4i */

#define SUN6I_HDMI_DDC_CLK_REG		0x520

/* DDC CLK bit fields are the same, but the formula is not */

#define SUN6I_HDMI_DDC_FIFO_DATA_REG	0x580

enum sun4i_hdmi_pkt_type {

	SUN4I_HDMI_PKT_AVI = 2,

	SUN4I_HDMI_PKT_END = 15,