Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c4642a47 authored by Junwei Zhang's avatar Junwei Zhang Committed by Alex Deucher
Browse files

drm/amd/amdgpu: add Polaris12 support (v3)



v2: agd: squash in various fixes
v3: agd: squash in:
drm/amdgpu: remove unnecessary smc sk firmware for polaris12

Signed-off-by: default avatarJunwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarKen Wang <Qingqing.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7f4c4f80
Loading
Loading
Loading
Loading
+3 −0
Original line number Diff line number Diff line
@@ -840,6 +840,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
				else if (type == CGS_UCODE_ID_SMU_SK)
					strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
				break;
			case CHIP_POLARIS12:
				strcpy(fw_name, "amdgpu/polaris12_smc.bin");
				break;
			default:
				DRM_ERROR("SMC firmware not supported\n");
				return -EINVAL;
+2 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ static const char *amdgpu_asic_name[] = {
	"STONEY",
	"POLARIS10",
	"POLARIS11",
	"POLARIS12",
	"LAST",
};

@@ -1277,6 +1278,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
	case CHIP_FIJI:
	case CHIP_POLARIS11:
	case CHIP_POLARIS10:
	case CHIP_POLARIS12:
	case CHIP_CARRIZO:
	case CHIP_STONEY:
		if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
+5 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@
#define FIRMWARE_STONEY		"amdgpu/stoney_uvd.bin"
#define FIRMWARE_POLARIS10	"amdgpu/polaris10_uvd.bin"
#define FIRMWARE_POLARIS11	"amdgpu/polaris11_uvd.bin"
#define FIRMWARE_POLARIS12	"amdgpu/polaris12_uvd.bin"

/**
 * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -98,6 +99,7 @@ MODULE_FIRMWARE(FIRMWARE_FIJI);
MODULE_FIRMWARE(FIRMWARE_STONEY);
MODULE_FIRMWARE(FIRMWARE_POLARIS10);
MODULE_FIRMWARE(FIRMWARE_POLARIS11);
MODULE_FIRMWARE(FIRMWARE_POLARIS12);

static void amdgpu_uvd_idle_work_handler(struct work_struct *work);

@@ -149,6 +151,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
	case CHIP_POLARIS11:
		fw_name = FIRMWARE_POLARIS11;
		break;
	case CHIP_POLARIS12:
		fw_name = FIRMWARE_POLARIS12;
		break;
	default:
		return -EINVAL;
	}
+5 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@
#define FIRMWARE_STONEY		"amdgpu/stoney_vce.bin"
#define FIRMWARE_POLARIS10	"amdgpu/polaris10_vce.bin"
#define FIRMWARE_POLARIS11         "amdgpu/polaris11_vce.bin"
#define FIRMWARE_POLARIS12         "amdgpu/polaris12_vce.bin"

#ifdef CONFIG_DRM_AMDGPU_CIK
MODULE_FIRMWARE(FIRMWARE_BONAIRE);
@@ -66,6 +67,7 @@ MODULE_FIRMWARE(FIRMWARE_FIJI);
MODULE_FIRMWARE(FIRMWARE_STONEY);
MODULE_FIRMWARE(FIRMWARE_POLARIS10);
MODULE_FIRMWARE(FIRMWARE_POLARIS11);
MODULE_FIRMWARE(FIRMWARE_POLARIS12);

static void amdgpu_vce_idle_work_handler(struct work_struct *work);

@@ -121,6 +123,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
	case CHIP_POLARIS11:
		fw_name = FIRMWARE_POLARIS11;
		break;
	case CHIP_POLARIS12:
		fw_name = FIRMWARE_POLARIS12;
		break;

	default:
		return -EINVAL;
+10 −3
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
						 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
		break;
	case CHIP_POLARIS11:
	case CHIP_POLARIS12:
		amdgpu_program_register_sequence(adev,
						 polaris11_golden_settings_a11,
						 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
@@ -608,6 +609,7 @@ static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
		num_crtc = 6;
		break;
	case CHIP_POLARIS11:
	case CHIP_POLARIS12:
		num_crtc = 5;
		break;
	default:
@@ -1589,6 +1591,7 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev)
		adev->mode_info.audio.num_pins = 8;
		break;
	case CHIP_POLARIS11:
	case CHIP_POLARIS12:
		adev->mode_info.audio.num_pins = 6;
		break;
	default:
@@ -2388,7 +2391,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
	int pll;

	if ((adev->asic_type == CHIP_POLARIS10) ||
	    (adev->asic_type == CHIP_POLARIS11)) {
	    (adev->asic_type == CHIP_POLARIS11) ||
	    (adev->asic_type == CHIP_POLARIS12)) {
		struct amdgpu_encoder *amdgpu_encoder =
			to_amdgpu_encoder(amdgpu_crtc->encoder);
		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
@@ -2822,7 +2826,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
		return -EINVAL;

	if ((adev->asic_type == CHIP_POLARIS10) ||
	    (adev->asic_type == CHIP_POLARIS11)) {
	    (adev->asic_type == CHIP_POLARIS11) ||
	    (adev->asic_type == CHIP_POLARIS12)) {
		struct amdgpu_encoder *amdgpu_encoder =
			to_amdgpu_encoder(amdgpu_crtc->encoder);
		int encoder_mode =
@@ -2992,6 +2997,7 @@ static int dce_v11_0_early_init(void *handle)
		adev->mode_info.num_dig = 6;
		break;
	case CHIP_POLARIS11:
	case CHIP_POLARIS12:
		adev->mode_info.num_hpd = 5;
		adev->mode_info.num_dig = 5;
		break;
@@ -3101,7 +3107,8 @@ static int dce_v11_0_hw_init(void *handle)
	amdgpu_atombios_crtc_powergate_init(adev);
	amdgpu_atombios_encoder_init_dig(adev);
	if ((adev->asic_type == CHIP_POLARIS10) ||
	    (adev->asic_type == CHIP_POLARIS11)) {
	    (adev->asic_type == CHIP_POLARIS11) ||
	    (adev->asic_type == CHIP_POLARIS12)) {
		amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
						   DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
		amdgpu_atombios_crtc_set_dce_clock(adev, 0,
Loading